CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
Figure 5-14. SDRAM Single Read Cycle (3/3)
(c) During on-page access (when latency = 2)
RD
TW
TREAD
TLATE
TLATE
Data
Address
Address
Column address
Address
Address
SDCLK (output)
BCYST (output)
SDCKE (output)
H
Command
SDRAS (output)
H
SDCAS (output)
CSn (output)
WE (output)
LDQM (output)
UDQM (output)
Note
(output)
Bank address (output)
A10 (output)
A0 to A9 (output)
D0 to D15 (I/O)
On-page
Note
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 1, 3, 4, 6
4.
The timing chart shown here is the timing when the previous cycle accessed another CS space
or when the bus was in an idle state. If access to the same CS space continues, a TW state is
not inserted (the BCYST signal becomes active in the TREAD state).
