CHAPTER 4 BUS CONTROL FUNCTION
96
User’s Manual U14359EJ4V0UM
4.2.1 Pin status during internal ROM, internal RAM, and peripheral I/O access
While accessing internal ROM and RAM, the address bus becomes undefined, and the data bus control signals are
not output and enter the high-impedance state. The external bus control signals become inactive.
While accessing peripheral I/O, the address bus outputs the address data of the on-chip peripheral I/O currently
being accessed, and the data bus control signals are not output and enter the high-impedance state. The external
bus control signals become inactive.
