CHAPTER 3 CPU FUNCTION
71
User’s Manual U14359EJ4V0UM
3.3.2
Operating mode specification
The operating mode is specified according to the status of the MODE0 to MODE2 pins. In an application system
fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins
are changed during operation.
(a)
µµµµ
PD703103A
MODE2
MODE1
MODE0
Operating Mode
Remarks
L
L
L
ROMless mode 0
16-bit data bus
L
L
H
Normal operation mode
ROMless mode 1
8-bit data bus
Other than above
Setting prohibited
(b)
µµµµ
PD703105A, 703106A, 703107A
MODE2
MODE1
MODE0
Operating Mode
Remarks
L
L
L
ROMless mode 0
16-bit data bus
L
L
H
ROMless mode 1
8-bit data bus
L
H
L
Single-chip mode 0
Internal ROM area is allocated
from address 000000H.
L
H
H
Normal operation mode
Single-chip mode 1
Internal ROM area is allocated
from address 100000H.
Other than above
Setting prohibited
(c)
µµµµ
PD70F3107A
MODE2/
V
PP
MODE1
MODE0
Operating Mode
Remarks
0 V
L
L
ROMless mode 0
16-bit data bus
0 V
L
H
ROMless mode 1
8-bit data bus
0 V
H
L
Single-chip mode 0
Internal ROM area is allocated
from address 000000H.
0 V
H
H
Normal operation mode
Single-chip mode 1
Internal ROM area is allocated
from address 100000H.
7.8 V
H
H/L
Flash memory programming mode
−
Other than above
Setting prohibited
Remark
L: Low-level input
H: High-level input
