User’s Manual U14359EJ4V0UM
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CHAPTER 15 RESET FUNCTIONS
When a low-level signal is input to the RESET pin, a system reset is effected and the hardware is initialized.
When the RESET signal level changes from low to high, the reset state is released and CPU starts program
execution. Register contents must be initialized as required in the program.
15.1 Features
The reset pin (RESET) incorporates a noise eliminator that uses analog delay (
≅
60 ns) to prevent malfunction due
to noise.
15.2 Pin Functions
During a system reset, most pins (all but the CLKOUT
Note
, RESET, X2, V
DD
, V
SS
, CV
DD
, CV
SS
, AV
DD
/AV
REF
, and
AV
SS
pins) enter the high-impedance state. Therefore, when memory is connected externally, a pull-up or pull-down
resistor must be connected to the specified pins of ports AL, AH, DL, CS, CT, CM, CD, and BD. If no resistor is
connected, external memory may be destroyed when these pins enter the high-impedance state.
For the same reason, the output pins of the internal peripheral I/O functions and other output ports should be
handled in the same manner.
Note
In ROMless modes 0 and 1, and in single-chip mode 1, the CLKOUT signal is output even during reset. In
single-chip mode 0, the CLKOUT signal is not output until the PMCCM register is set.
The operation status of each pin during reset is shown below (Table 15-1).
Table 15-1. Operation Status of Each Pin During Reset
Pin State
Pin Name
Single-Chip Mode 0
Single-Chip Mode 1
ROMless Mode 0
ROMless Mode 1
A0 to A15, A16 to A25, D0 to D15,
CS0 to CS7, RAS1, RAS3, RAS4,
RAS6, LWR, UWR, LCAS, UCAS,
LDQM, UDQM, RD, WE, OE,
BCYST, WAIT, HLDAK, HLDRQ,
REFREQ, SELFREF, SDCKE,
SDCLK, SDCAS, SDRAS
(Port mode)
High impedance
CLKOUT
(Port mode)
Operating
Ports 0 to 5, 7, BD
(Input)
Port pin
Ports AL, AH, DL, CM,
CT, CS, CD
(Input)
(Control mode)
