CHAPTER 2 PIN FUNCTIONS
53
User’s Manual U14359EJ4V0UM
(8) PBD0 to PBD3 (Port BD) ··· 3-state I/O
PBD0 to PBD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as DMA acknowledge outputs.
The operation mode can be set to port or control in 1-bit units, specified by the port BD mode control register
(PMCBD).
(a) Port mode
PBD0 to PBD3 can be set to input or output in 1-bit units using the port BD mode register (PMBD).
(b) Control mode
PBD0 to PBD3 can be set to port/control mode in 1-bit units using the PMCBD register.
(i)
DMAAK0 to DMAAK3 (DMA acknowledge) ··· output
These signals show that a DMA service request was granted. They correspond to DMA channel 0 to
3, respectively, and operate independently of each other.
These signals become active only when external memory is being accessed. When DMA transfers
are being executed between internal RAM and internal peripheral I/O, they do not become active.
These signals are activated at the falling edge of the CLKOUT signal in the T0, T1R, T1FH state of
the DMA cycle, and maintained at an active level during DMA transfers.
(9) PCM0 to PCM5 (Port CM) ··· 3-state I/O
PCM0 to PCM5 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as the wait insertion signal input,
system clock output, bus hold control signal, refresh request signal output for DRAM, and self-refresh request
signal input.
The operation mode can be set to port or control in 1-bit units, specified by the port CM mode control register
(PMCCM).
(a) Port mode
PCM0 to PCM5 can be set to input or output in 1-bit units using the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM5 can be set to port/control mode in 1-bit units using the PMCCM register.
(i)
WAIT (Wait) ··· input
This is the control signal input pin at which a data wait is inserted in the bus cycle. The WAIT signal
can be input asynchronously to the CLKOUT signal. When the CLKOUT signal rises, sampling is
executed. When the set/hold time is not terminated within the sampling timing, wait insertion may
not be executed.
(ii) CLKOUT (Clock output) ··· output
This is the internal system clock output pin. In single-chip mode 0, because port mode is entered
during the reset period, output does not occur from the CLKOUT pin. CLKOUT output can be
executed by setting the port CM mode control register (PMCCM) and the port CM function control
register (PFCCM).
