CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
Figure 6-12. Timing of 2-Cycle DMA Transfer (EDO DRAM
→
→
→
→
SRAM) (3/3)
(c) Block transfer mode
CLKOUT (output)
DMARQx (input)
DMAAKx (output)
TCx (output)
Address (output)
Input DMA
request signal
BCYST (output)
LCAS/LWR (output)
UCAS/UWR (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Address
Data
TI
TI
TI
TI
TO
T1R
T2R T2R
T1
T2
T1
T1W
T1
T2W
T2
T2
TRPW
Note 3
T1
T2
TE
Data
Data
Data
Data
Address
TE
TI
T1R
TB
T2W
T2
T1W
T1
Data
RASm (output) of
DRAM area
CSn (output) of
other area
CSn (output) of
SRAM area
Note 1
Row
Col.
Col.
Note 2
Notes 1.
TRPW is always inserted for one or more cycles.
2.
This idle state (TI) is independent of the BCC register setting.
3.
In the case of the RAS hold mode
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
4.
Col.: Column address
Row: Row address
