CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
245
User’s Manual U14359EJ4V0UM
Figure 6-16. Timing of Flyby Transfer (DRAM
→
→
→
→
External I/O) (1/3)
(a) Block transfer mode
TO
TI
TI
TI
TI
T1FH
Note
TRPW
T2FH
T1
T1FH
TF
TE
TF
TE
T2
T1FH
TB
T1FH
TW
A0 to A25 (output)
D0 to D15 (I/O)
DMARQx (input)
CLKOUT (output)
BCYST (output)
RASm (output) of
DRAM area
CSn (output) of
external I/O area
OE (output)
RD (output)
IORD (output)
IOWR (output)
WAIT (input)
WE (output)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
LWR/LCAS (output)
UWR/UCAS (output)
Col.
Col.
Row
Data
Data
H
H
H
H
Note
TRPW is always inserted for one or more cycles.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n
≠
m)
4.
Col.: Column address
Row: Row address
