CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
239
User’s Manual U14359EJ4V0UM
Figure 6-13. Timing of 2-Cycle DMA Transfer (SRAM
→
→
→
→
SDRAM) (2/3)
(b) Single-step transfer mode
SDCLK (output)
DMARQx (input)
DMAAKx (output)
TCx (output)
Address (output)
Internal DMA
request signal
BCYST (output)
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM (output)
UDQM (output)
SDCKE (output)
D0 to D15 (I/O)
Address
Col.
Col.
Data
H
TI
TI
TI
TI
TO
T1R
T1W T2W T2W
T2R
TI
TI
T1
T2
T1
TI
T1
TI
T2
TI
T2
T1
T2
TW
T1W
TW
T2
TACT TWR
T2W
TWR
TWE
TWPRE
Data
Data
Data
Address
T2W T2W
TWE
TWPRE
T2W T2W
TI
T1
T1R
T1
T2R
T2
Data
Data
Data
Data
CSn (output) of
other area
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
Row
Note
Note
Note
This idle state (TI) is independent of the BCC register setting.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, x = 0 to 3
4.
Col.: Column address
Row: Row address
