CHAPTER 9 CLOCK GENERATION FUNCTION
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User’s Manual U14359EJ4V0UM
9.4
PLL Lockup
The lockup time (frequency stabilization time) is the time from when the power is turned on or software STOP
mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called
the unlocked state, and the stabilized state is called the locked state.
The lock register (LOCKR) has a lock flag that reflects the stabilized state of the PLL frequency.
This register is read-only in 8-bit or 1-bit units.
Caution
If the phase is locked, the LOCK flag is cleared to 0. If it is unlocked later because of a standby
status, the LOCK flag is set to 1. If the phase is unlocked by a cause other than the standby
status, however, the LOCK flag is not affected (LOCK = 0).
7
6
5
4
3
2
1
<0>
Address
After reset
LOCKR
0
0
0
0
0
0
0
LOCK
FFFFF824H 0000000xB
Bit position
Bit name
Function
0
LOCK
Lock Status Flag
This is a read-only flag that indicates the PLL lock state. This flag holds the value 0
as long as a lockup state is maintained and is not initialized by a system reset.
0: Indicates that the PLL is locked.
1: Indicates that the PLL is not locked (unlock state).
If the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control
processing that depends on software execution speed, such as real-time processing, be sure to judge the LOCK flag
by software immediately after operation begins so that processing does not begin until after the clock stabilizes.
On the other hand, static processing such as the setting of internal hardware or the initialization of register data or
memory data can be executed without waiting for the LOCK flag to be reset.
The relationship between the oscillation stabilization time (the time from when the resonator starts to oscillate until
the input waveform stabilizes) when a resonator is used, and the PLL lockup time (the time until frequency stabilizes)
is shown below.
Oscillation stabilization time < PLL lockup time.
