CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
184
User’s Manual U14359EJ4V0UM
Figure 5-14. SDRAM Single Read Cycle (1/3)
(a) During off-page access (when latency = 2)
TACT
ACT
RD
TW
TREAD
TLATE
TLATE
Data
Address
Address
Address
Address
Column address
Row
address
Address
Address
Bank
address
Address
Row
address
SDCLK (output)
BCYST (output)
SDCKE (output)
H
Command
SDRAS (output)
SDCAS (output)
CSn (output)
WE (output)
LDQM (output)
UDQM (output)
Note
(output)
Bank address (output)
A10 (output)
A0 to A9 (output)
D0 to D15 (I/O)
Off-page
Note
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 1, 3, 4, 6
