NEC V850E/MA1, User Manual

Page: 195 / 567

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
195
User’s Manual U14359EJ4V0UM
Figure 5-16. SDRAM Access Timing (4/4)
(d) Write timing (8-bit bus width word access, bank change, BCW = 1, latency = 2)
SDCLK (output)
Note (output)
A10 (output)
A0 to A9 (output)
BCYST (output)
Bank address (output)
SDRAS (output)
SDCAS (output)
CSn (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
SDCKE (output)
D0 to D7 (I/O)
Add. Add. Add. Add. Add. Add. Add. Add. Add. Add. Add. Add. Add.
Add. Add. Add. Add. Add. Add. Bnk.
Col. Col. Col.
Col.
Bnk.
Data Data Data Data Data Data Data Data
H
Data Data Data
TW TACT TWR TWR TWR TWR
BCW
Bank A write
TWPRE TWE TW TACT TW TACT TWR TWR TWR TWR
BCW BCW
TWPRE TWE TREAD TREAD TREAD TREAD TLATE TLATE
Bank B write Bank A read
Bank A active
command
Bank A write
command
Bank A write
command
Bank A write
command
Bank A write
command
Bank A precharge
command
Bank B active
command
Bank B write
command
Bank B write
command
Bank B write
command
Bank B write
command
Bank B precharge
command
Bank A active
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Add.
Bnk.
Add.
Bnk. Bnk.
Add. Add. Add. Add. Add. Add.
Row
Add.
Row
Col. Col. Col.
Col.
Add. Row Col. Col. Col.
Col.
Add. Row
Row
Add. Add.
Row
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle
{
indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address