CHAPTER 11 SERIAL INTERFACE FUNCTION
User’s Manual U14359EJ4V0UM
381
(7) Receive data noise filter
The RXDn signal is sampled at the rising edge of the prescaler output clock. If the same sampling value is
obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data
not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see
Figure 11-
11
). See
11.2.6 (1) (a) Basic clock (Clock)
regarding the basic clock.
Also, since the circuit is configured as shown in Figure 11-10, internal processing during a receive operation
is delayed by up to 2 clocks according to the external signal status.
Figure 11-10. Noise Filter Circuit
RXDn
Q
Clock
In
LD_EN
Q
In
Internal signal A
Internal signal B
Match detector
Remark
n = 0 to 2
Figure 11-11. Timing of RXDn Signal Judged as Noise
Internal signal A
Clock
RXDn (input)
Internal signal B
Match
Mismatch
(judged as noise)
Mismatch
(judged as noise)
Match
Remark
n = 0 to 2
