CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
(1) SDRAM single read cycle
The SDRAM single read cycle is a cycle for reading from SDRAM by executing a load instruction (LD) for the
SDRAM area, by fetching an instruction, or by 2-cycle DMA transfer.
In the SDRAM single read cycle, the active command (ACT) and read command (RD) are issued for SDRAM
in that order. During on-page access, however, only the read command is issued and the precharge
command and active command are not issued. When a page change occurs in the same bank, the
precharge command (PR) is issued before the active command.
The timing to sample data is synchronized with rising of the UDQM and LDQM signals.
A one-state TW cycle is always inserted immediately before every read command, which is activated by the
CPU.
The number of idle states set by the bus cycle control register (BCC) are inserted before the read cycle (no
idle states are inserted, however, if BCn1 and BCn0 are 00) (n = 1, 3, 4, 6). The timing charts of the SDRAM
single read cycle are shown below.
Caution
When executing a write access to SRAM or external I/O after read accessing SDRAM, data
conflict may occur depending on the SDRAM data output float delay time. In such a case,
avoid data conflict by inserting an idle state in the SDRAM space via a setting in the BCC
register.
