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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
(3) Refresh timing
Figure 5-9. CBR Refresh Timing
T1
T2
TRRW
WAIT (input)
D0 to D15 (I/O)
IOWR (output)
IORD (output)
LWR/LCAS (output)
UWR/UCAS (output)
OE (output)
RD (output)
CSn/RASm (output)
BCYST (output)
A0 to A25 (output)
REFRQ (output)
CLKOUT (output)
TRCW
T3
TRCW
Note 1
T4
TI
Note 2
TI
Note 2
WE (output)
Notes 1.
The TRCW cycle is always inserted for one or more clocks, irrespective of the setting of bits RCW2 to
RCW0 of the RWC register.
2.
This idle state (TI) is independent of the BCC register setting.
Remark
n = 0 to 7, m = 1, 3, 4, 6