CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
4.8.2 Bus hold procedure
The procedure of the bus hold function is illustrated below.
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests held pending
<3> End of current bus cycle
<4> Transition to bus idle state
<5> HLDAK = 0
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Pending bus cycle start requests released
<9> Start of bus cycle
Normal state
Bus hold state
Normal state
HLDAK (output)
HLDRQ (input)
<1> <2>
<3><4> <5>
<6> <7><8><9>
4.8.3 Operation in power-save mode
In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not
set since the HLDRQ pin cannot be acknowledged even if it becomes active.
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus
hold state is set. When the HLDRQ pin becomes inactive after that, the HLDAK pin also becomes inactive. As a
result, the bus hold state is cleared and the HALT mode is set again.
