CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
241
User’s Manual U14359EJ4V0UM
Figure 6-14. Timing of 2-Cycle DMA Transfer (SDRAM
→
→
→
→
SRAM) (1/3)
(a) Single transfer mode
SDCLK (output)
DMARQx (input)
DMAAKx (output)
TCx (output)
Address (output)
Internal DMA
request signal
BCYST (output)
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM/LWR (output)
UDQM/UWR (output)
SDCKE (output)
D0 to D15 (I/O)
Address
Col.
Col.
H
TI
TI
TI
TI
TO
T1R
T2R
TI
TI
T1
T2
T1
TI
TI
T1
T1
TI
T2
T2
TO
T2
T2
TW
T1W
TW
TACT
TW
TI
TW
Data
Data
Address
T1W
TREAD
T2R
TLATE
T2R
TLATE
T2R
TREAD
T2W
TLATE
T2W
TLATE
T2W
T2W
T1R
T2R
TI
T1
T2
T1
Data
Data
Data
Data
Data
Data
CSn (output) of
other area
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
Row
Note
Note
Note
This idle state (TI) is independent of the BCC register setting.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, x = 0 to 3
4.
Col.: Column address
Row: Row address
