CHAPTER 4 BUS CONTROL FUNCTION
139
User’s Manual U14359EJ4V0UM
4.9
Bus Priority Order
There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle, and refresh cycle.
In order of priority, bus hold is the highest, followed by the refresh cycle, DMA cycle, operand data access, and
instruction fetch, in that order.
An instruction fetch may be inserted between a read access and write access during a read modify write access.
Also, an instruction fetch may be inserted between bus accesses when the CPU bus clock is used.
Table 4-2. Bus Priority Order
Priority
Order
External Bus Cycle
Bus Master
Bus hold
External device
Refresh cycle
DRAM controller
DMA cycle
DMA controller
Operand data access
CPU
High
Low
Instruction fetch
CPU