CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
6.17 Cautions
(1) Memory boundary
The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
objects (external memory, internal RAM, or peripheral I/O) during DMA transfer.
(2) Transfer of misaligned data
DMA transfer of 16-bit bus width misaligned data is not supported. If the source or the destination address is
set to an odd address, the LSB of the address is forcibly handled as "0".
(3) Bus arbitration for CPU
When an external device is targeted for DMA transfer, the CPU can access the internal ROM and internal
RAM (if they are not subject to DMA transfer).
When DMA transfer is executed between the on-chip peripheral I/O and internal RAM, the CPU can access
the internal ROM.
(4) DMAAKn signal output
When the transfer object is internal RAM, the DMAAKn signal is not output during a DMA cycle for internal
RAM (for example, if 2-cycle transfer is performed from internal RAM to an external memory, the DMAAKn
signal is output only during a DMA write cycle for the external memory).
(5) DMA start factors
Do not start two or more DMA channels with the same factor. If two or more DMA channels are started with
the same factor, the DMA channel with the lower priority may be accepted before the DMA channel with the
higher priority.
6.17.1 Interrupt factors
DMA transfer is interrupted if the following factors are issued.
•
Bus hold
•
Refresh cycle
If the factor that is interrupting DMA transfer disappears, DMA transfer promptly restarts.
6.18 DMA Transfer End
When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
