CHAPTER 4 BUS CONTROL FUNCTION
138
User’s Manual U14359EJ4V0UM
(4) SDRAM (when written, when bus hold request acknowledged during on-page access)
TPRE
Note 2
TW
TACT
D0 to D15 (I/O)
WE (output)
OE (output)
RD (output)
SDCAS (output)
SDRAS (output)
CSn (output)
BCYST (output)
A0 to A9 (output)
A10 (output)
Bank address (output)
SDCLK (output)
TWPRE TWE
TBCW TWR
TWR
TW
TH
TH
TI
Note 1
TI
Note 1
HLDRQ (input)
HLDAK (output)
Note 3
(output)
SDCKE (output)
LDQM (output)
UDQM (output)
H
Address
Address
Bank
address
Row
address
Undefined
Undefined
Undefined
Undefined
Data
Data
BCW
Address
Address
Address
Row
address
Column address
Column address
Notes 1.
This idle state (TI) is independent of the BCC register setting.
2.
The all bank precharge command is always executed.
3.
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 1, 3, 4, 6
