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CHAPTER 12 A/D CONVERTER
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User’s Manual U14359EJ4V0UM
12.7 Operation in External Trigger Mode
In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing.
The ADTRG pin has an alternate function as the P37 and INTP123 pins. To set the external trigger mode, set the
PMC37 bit of the PMC3 register to 1 and bits TRG2 to TRG0 of the ADM1 register to 110.
For the valid edge of the external input signal during the external trigger mode, the rising edge, falling edge, or both
rising and falling edges can be specified using bits ES1231 and ES1230 of the INTM3 register. For details, see
7.3.9
(1) External interrupt mode registers 1 to 4 (INTM1 to INTM4)
.
12.7.1 Select mode operations (external trigger select)
In this mode, one analog input (ANI0 to ANI3) specified by the ADM0 register is A/D converted. The conversion
results are stored in the ADCRn register corresponding to the analog input. There are two select modes: 1-buffer
mode and 4-buffer mode, according to the storing method of the A/D conversion results (n = 0 to 3).
(1) 1-buffer mode (external trigger select: 1-buffer)
In this mode, one analog input is A/D converted using the ADTRG signal as a trigger. The conversion results
are stored in one ADCRn register. The analog input and the A/D conversion results register correspond one
to one. The A/D conversion end interrupt (INTAD) is generated for each A/D conversion, and A/D conversion
is stopped.
Trigger
Analog Input
A/D Conversion Result Register
ADTRG signal
ANIn
ADCRn
While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from
the ADTRG pin.
This mode is most appropriate for applications in which the results are read after each A/D conversion.
Figure 12-15. Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer)
ANI0
ANI1
ANI2
ANI3
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D converter
ADTRG
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(2)
The external trigger is generated
(3)
ANI2 is A/D converted
(4)
The conversion result is stored in ADCR2
(5)
The INTAD interrupt is generated