NEC V850E/MA1, User Manual

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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
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User’s Manual U14359EJ4V0UM
7.7 Interrupt Latency Time
The V850E/MA1 interrupt latency time (from interrupt request generation to start of interrupt servicing) is
described below.
Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline)
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgement operation
Instruction (start instruction of
interrupt service routine)
Interrupt request
IF ID EX DF WB
IFX IDX
4 system clocks
IF
Interleave access
Note
IF ID EX
INT1 INT2 INT3 INT4
Note For interleave access, refer to 8.1.2 2-clock branch in V850E1 User’s Manual Architecture
(U14559E) .
Remark INT1 to INT4: Interrupt acknowledgement processing
IFX: Invalid instruction fetch
IDX: Invalid instruction decode
Interrupt latency time (internal system clock)
External interrupt Internal
interrupt
INTP0nm INTP1nm
Condition
Minimum 4 7 +
Analog delay time
4 +
Analog delay time
Maximum 7
Note
10 +
Analog delay time
7 +
Analog delay time
The following cases are exceptions.
•
In IDLE/software STOP mode
•
External bus access
•
Two or more interrupt request non-sample
instructions are executed in succession
•
Access to peripheral I/O register
Note When LD instruction is executed to the internal ROM
Remark n = 0 to 3, m = 0, 1