CHAPTER 3 CPU FUNCTION
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User’s Manual U14359EJ4V0UM
3.4.5
Area
(1) Internal ROM area
(a) Memory map (
µµµµ
PD703105A, 703106A, 703107A, 70F3107A)
1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved.
<1>
µµµµ
PD703105A, 703106A
128 KB are provided at the following addresses as physical internal ROM (mask ROM).
•
In single-chip mode 0: Addresses 000000H to 01FFFFH
•
In single-chip mode 1: Addresses 100000H to 11FFFFH
<2>
µµµµ
PD703107A
256 KB are provided at the following addresses as physical internal ROM (mask ROM).
•
In single-chip mode 0: Addresses 000000H to 03FFFFH
•
In single-chip mode 1: Addresses 100000H to 13FFFFH
<3>
µµµµ
PD70F3107A
256 KB are provided at the following addresses as physical internal ROM (flash memory).
•
In single-chip mode 0: Addresses 000000H to 03FFFFH
•
In single-chip mode 1: Addresses 100000H to 13FFFFH
(b) Interrupt/exception table
The V850E/MA1 increases the interrupt response speed by assigning handler addresses corresponding
to interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the
internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the
handler address, and the program written in that memory is executed. Table 3-3 shows the sources of
interrupts/exceptions, and the corresponding addresses.
Remark
When in ROMless modes 0 and 1, in single-chip mode 1, or in the case of the
µ
PD703103A,
in order to restore correct operation after reset, provide a handler address to the reset routine
at address 0 of the external memory.
