User’s Manual U14359EJ4V0UM
25
LIST OF TABLES (1/2)
Table No.
Title
Page
3-1
Program Registers.......................................................................................................................................... 67
3-2
System Register Numbers.............................................................................................................................. 68
3-3
Interrupt/Exception Table ............................................................................................................................... 78
4-1
Bus Cycles in Which Wait Function Is Valid ................................................................................................. 125
4-2
Bus Priority Order ......................................................................................................................................... 139
5-1
Example of DRAM and Address Multiplex Width.......................................................................................... 161
5-2
Interval Factor Setting Examples.................................................................................................................. 172
5-3
Example of Interval Factor Settings.............................................................................................................. 198
6-1
Relationship Between Transfer Type and Transfer Object ........................................................................... 255
6-2
External Bus Cycles During DMA Transfer................................................................................................... 256
6-3
Number of Minimum Execution Clocks in DMA Cycle .................................................................................. 261
7-1
Interrupt/Exception Source List .................................................................................................................... 265
9-1
Clock Generator Operation Using Power-Save Control................................................................................ 308
9-2
Operation Status in HALT Mode................................................................................................................... 312
9-3
Operation After HALT Mode Is Released by Interrupt Request.................................................................... 313
9-4
Operation Status in IDLE Mode .................................................................................................................... 315
9-5
Operation After IDLE Mode Is Released by Interrupt Request ..................................................................... 316
9-6
Operation Status in Software STOP Mode ................................................................................................... 318
9-7
Operation After Software STOP Mode Is Released by Interrupt Request .................................................... 319
9-8
Counting Time Examples (f
XX
= 10
×
f
X
) ....................................................................................................... 322
10-1
Timer C Configuration .................................................................................................................................. 324
10-2
TO0n Output Control .................................................................................................................................... 340
10-3
Timer D Configuration .................................................................................................................................. 349
11-1
Generated Interrupts and Default Priorities .................................................................................................. 369
11-2
Reception Error Causes ............................................................................................................................... 378
11-3
Baud Rate Generator Setting Data............................................................................................................... 386
11-4
Maximum and Minimum Allowable Baud Rate Error .................................................................................... 388
15-1
Operation Status of Each Pin During Reset ................................................................................................. 504
15-2
Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset ............................................... 506
