CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
5.2
Page ROM Controller (ROMC)
The page ROM controller (ROMC) is provided for accessing ROM (page ROM) with a page access function.
Addresses are compared with the immediately preceding bus cycle and wait control for normal access (off-page)
and page access (on-page) is executed. This controller can handle page widths from 8 to 128 bytes.
5.2.1 Features
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Direct connection to 8-bit/16-bit page ROM supported
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For 16-bit bus width: 4/8/16/32/64-word page access supported
For 8-bit bus width: 8/16/32/64/128-word page access supported
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Page ROM is accessed in a minimum of 2 states.
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On-page judgment function
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Addresses to be compared can be changed by setting the PRC register.
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Up to 7 states of programmable data waits can be inserted during an on-page cycle by setting the PRC
register.
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Up to 7 states of programmable data waits can be inserted during an off-page cycle by setting the DWC0 and
DWC1 registers.
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Waits can be controlled via WAIT pin input.
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DMA flyby cycle can be activated (page ROM
→
external I/O)
