NEC V850E/MA1, User Manual

Page: 193 / 567

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
193
User’s Manual U14359EJ4V0UM
Figure 5-16. SDRAM Access Timing (2/4)
(b) Read timing (8-bit bus width word access, page change, BCW = 2, latency = 2)
Data Data Data Data Data Data Data Data
TA TW TACT TBCW TREAD TREAD TREAD TREAD TBCW TLATE TLATE TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE TPREC
BCW BCW BCW
Add. Add.
Row
Col. Col.
Add. Col. Col.
Col. Col. Col. Col. Add.
Row
Add. Add. Add. Add. Add. Add.
Add. Add. Add. Add.
SDCLK (output)
Note (output)
A10 (output)
A0 to A9 (output)
BCYST (output)
Bank address (output)
SDRAS (output)
SDCAS (output)
CSn (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
SDCKE (output)
D0 to D7 (I/O)
H
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
(On-page)
Bank A
precharge
command
Bank A active
command
Bank A
active
command
(On-page)
(Page change)
Add. Bnk.
Add. Add.
Add. Row
Bnk. Bnk.
Add. Add. Row
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle
{
indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address