CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
Figure 6-19. DRAM Access Timing During DMA Flyby Transfer (3/4)
(c) External I/O
→
→
→
→
DRAM (when no waits are inserted)
TRPW
Note 1
T1
Column address
Row address
Data
WAIT (input)
D0 to D15 (I/O)
IOWR (output)
IORD
Note 2
(output)
LWR/LCAS (output)
UWR/UCAS (output)
WE (output)
OE (output)
RD (output)
CSn/RASm (output)
BCYST (output)
A0 to A25 (output)
CLKOUT (output)
TE
TCPW
Note 1
T2
TB
TE
DMAAKx (output)
Column address
Data
Note 4
Note 4
Note 4
Note 4
Note 3
Notes 1.
TRPW and TCPW are always inserted for one or more cycles.
2.
During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
3.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this cycle.
4.
The rise timing of this write cycle is different from that of a normal EDO DRAM write cycle.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
