CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
User’s Manual U14359EJ4V0UM
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Bit position
Bit name
Function
5
ACTLVn
(n = 0 to 3)
Active Level
Specifies the active level for external pulse output (TO0n) (n = 0 to 3).
0: Active level is low level
1: Active level is high level
Caution The initial value of the ACTLVn bit is 1.
4
ETIn
(n = 0 to 3)
External Input
Specifies a switch between the external and internal count clock.
0: Specifies the input clock (internal). The count clock can be selected
according to the CSn2 to CSn0 bits of TMCCn0 (n = 0 to 3).
1: Specifies the external clock (TI0n0). The valid edge can be selected
according to the TESn1 and TESn0 bit specifications of SESCn (n = 0 to 3).
3
CCLRn
(n = 0 to 3)
Compare Clear Enable
Sets whether the clearing of TMCn is enabled or disabled during a compare
operation (n = 0 to 3).
0: Clearing is disabled
1: Clearing is enabled (if CCCn0 and TMCn match during a compare operation,
TMCn is cleared)
1
CMSn1
(n = 0 to 3)
Capture/Compare Mode Select
Selects the operation mode of the capture/compare register (CCCn1) (n = 0 to 3).
0: The register operates as a capture register
1: The register operates as a compare register
0
CMSn0
(n = 0 to 3)
Capture/Compare Mode Select
Selects the operation mode of the capture/compare register (CCCn0) (n = 0 to 3).
0: The register operates as a capture register
1: The register operates as a compare register
Remarks 1.
A reset takes precedence for the flip-flop of the TO0n output (n = 0 to 3).
2.
When the A/D converter is set to timer trigger mode, the match interrupt of the compare registers
becomes a start trigger for A/D conversion, and the conversion operation begins. At this time, the
compare register match interrupt also functions as a compare register match interrupt for the
CPU. To prevent the generation of a compare register match interrupt for the CPU, disable
interrupts using the interrupt mask bits (P00MK0, P00MK1, P01MK0, and P01MK1) of the
interrupt control registers (P00IC0, P00IC1, P01IC0, and P01IC1).