CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
Figure 6-9. Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer (2/2)
(b) SRAM
→
→
→
→
External I/O (BCC register setting for SRAM: BCn1, BCn0 = 11B)
(BCC register setting for external I/O: BCn1, BCn0 = 00B)
T1
T2
A0 to A25 (output)
D0 to D15 (I/O)
DMARQx (input)
CLKOUT (output)
BCYST (output)
CSn/RASm (output)
of SRAM area
CSn/RASm (output)
of external I/O area
OE (output)
RD (output)
IORD (output)
IOWR (output)
WAIT (input)
WE (output)
DMAAKx (output)
TCx (output)
LBE (output)
UBE (output)
LWR/LCAS (output)
UWR/UCAS (output)
TI
Note 2
TI
Note 1
TI
Note 1
TI
Note 1
T1
T2
Address
Address
Data
Data
Notes 1.
This idle state (TI) is inserted by means of a BCC register setting.
2.
This idle state (TI) is independent of the BCC register setting.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
