SCI/LIN Control Registers
1667
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7 SCI/LIN Control Registers
The SCI/LIN module registers are based on the SCI registers, with added functionality registers enabled
by the LIN MODE bit in the SCIGCR1 register.
These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI/LIN is controlled and
accessed through the registers listed in
. Among the features that can be programmed are the
LIN protocol mode, communication and timing modes, baud rate value, frame format, DMA requests, and
interrupt configuration. The base address for the control registers is FFF7 E400h for LIN1/SCI1 and
FFF7 E600h for LIN2/SCI2.
Table 29-10. SCI/LIN Control Registers
Offset
Acronym
Register Description
Section
00h
SCIGCR0
SCI Global Control Register 0
04h
SCIGCR1
SCI Global Control Register 1
08h
SCIGCR2
SCI Global Control Register 2
0Ch
SCISETINT
SCI Set Interrupt Register
10h
SCICLEARINT
SCI Clear Interrupt Register
14h
SCISETINTLVL
SCI Set Interrupt Level Register
18h
SCICLEARINTLVL
SCI Clear Interrupt Level Register
1Ch
SCIFLR
SCI Flags Register
20h
SCIINTVECT0
SCI Interrupt Vector Offset 0
24h
SCIINTVECT1
SCI Interrupt Vector Offset 1
28h
SCIFORMAT
SCI Format Control Register
2Ch
BRS
Baud Rate Selection Register
30h
SCIED
Receiver Emulation Data Buffer
34h
SCIRD
Receiver Data Buffer
38h
SCITD
Transmit Data Buffer
3Ch
SCIPIO0
SCI Pin I/O Control Register 0
40h
SCIPIO1
SCI Pin I/O Control Register 1
44h
SCIPIO2
SCI Pin I/O Control Register 2
48h
SCIPIO3
SCI Pin I/O Control Register 3
4Ch
SCIPIO4
SCI Pin I/O Control Register 4
50h
SCIPIO5
SCI Pin I/O Control Register 5
54h
SCIPIO6
SCI Pin I/O Control Register 6
58h
SCIPIO7
SCI Pin I/O Control Register 7
5Ch
SCIPIO8
SCI Pin I/O Control Register 8
60h
LINCOMPARE
LIN Compare Register
64h
LINRD0
LIN Receive Buffer 0 Register
68h
LINRD1
LIN Receive Buffer 1 Register
6Ch
LINMASK
LIN Mask Register
70h
LINID
LIN Identification Register
74h
LINTD0
LIN Transmit Buffer 0
78h
LINTD1
LIN Transmit Buffer 1
7Ch
MBRS
Maximum Baud Rate Selection Register
90h
IODFTCTRL
Input/Output Error Enable Register