Architecture
1834
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
EMAC/MDIO Module
32.2.9.1.3 MAC Receiver
The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into
the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM.
32.2.9.1.4 Transmit DMA Engine
The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the
CPU through the bus arbiter in the EMAC control module.
32.2.9.1.5 Transmit FIFO
The transmit FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers
data in preparation for transmission.
32.2.9.1.6 MAC Transmitter
The MAC transmitter formats frame data from the transmit FIFO and transmits the data using the
CSMA/CD access protocol. The frame CRC can be automatically appended, if required. The MAC
transmitter also detects transmission errors and passes statistics to the statistics registers.
32.2.9.1.7 Statistics Logic
The Ethernet statistics are counted and stored in the statistics logic RAM. This statistics RAM keeps track
of 36 different Ethernet packet statistics.
32.2.9.1.8 State RAM
State RAM contains the head descriptor pointers and completion pointers registers for both transmit and
receive channels.
32.2.9.1.9 EMAC Interrupt Controller
The interrupt controller contains the interrupt related registers and logic. The 26 raw EMAC interrupts are
input to this submodule and masked module interrupts are output.
32.2.9.1.10 Control Registers and Logic
The EMAC is controlled by a set of memory-mapped registers. The control logic also signals transmit,
receive, and status related interrupts to the CPU through the EMAC control module.
32.2.9.1.11 Clock and Reset Logic
The clock and reset submodule generates all the EMAC clocks and resets. For more details on reset
capabilities, see
32.2.9.2 EMAC Module Operational Overview
After reset, initialization, and configuration, the host may initiate transmit operations. Transmit operations
are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the
state RAM block. The transmit DMA controller then fetches the first packet in the packet chain from
memory. The DMA controller writes the packet into the transmit FIFO in bursts of 64-byte cells. When the
threshold number of cells, configurable using the TXCELLTHRESH bit in the FIFO control register
(FIFOCONTROL), have been written to the transmit FIFO, or a complete packet, whichever is smaller, the
MAC transmitter then initiates the packet transmission. The SYNC block transmits the packet over the MII
or RMII interfaces in accordance with the 802.3 protocol. Transmit statistics are counted by the statistics
block.
