Basic Operation
1529
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.2.7 General-Purpose I/O
All of the SPI pins may be programmed via the SPIPCx control registers to be either functional or general-
purpose I/O pins.
If the SPI function is to be used, application software must ensure that at least the SPICLK pin and the
SOMI and/or SIMO pins are configured as SPI functional pins, and not as GIO pins, or else the SPI state
machine will be held in reset, preventing SPI transactions.
SPI pins support:
•
internal pull-up resistors
•
internal pull-down resistors
•
open-drain or push-pull mode
•
input-buffer enabling/disabling (controlled by the PULDIS and PSEL bits)
28.2.8 Low-Power Mode
The SPI can be put into either local or global low-power mode. Global low-power mode is asserted by the
system and is not controlled by the SPI. During global low-power mode, all clocks to the SPI are turned
off, making the module completely inactive.
Local low-power mode is asserted by setting the POWERDOWN (SPIGCR1[8]) bit; setting this bit stops
the clocks to the SPI internal logic and registers. Setting the POWERDOWN bit causes the SPI to enter
local low-power mode and clearing the POWERDOWN bit causes SPI to exit from local low-power mode.
All registers remain accessible during local power-down mode, since the clock to the SPI registers is
temporarily re-enabled for each access. RAM buffers are also accessible during low power mode.
NOTE:
Since entering a low-power mode has the effect of suspending all state-machine activities,
care must be taken when entering such modes to ensure that a valid state is entered when
low-power mode is active. Application software must ensure that a low power mode is not
entered during a data transfer.
28.2.9 Safety Features
28.2.9.1 Detection of Slave Desynchronization (Master Only)
When a slave supports generation of an enable signal (ENA), desynchronization can be detected. With
the enable signal a slave indicates to the master that it is ready to exchange data. A desynchronization
can occur if one or more clock edges are missed by the slave. In this case the slave may block the SOMI
line until it detects clock edges corresponding to the next data word. This would corrupt the data word of
the desynchronized slave and the consecutive data word. A configurable 8-bit time-out counter
(T2EDELAY), which is clocked with SPICLK, is implemented to detect this slave malfunction. After the
transmission has finished (end of last bit transferred: either last data bit or parity bit) the counter is started.
If the ENA signal generated by the slave does not become inactive before the counter overflows, the
DESYNC flag is set and an interrupt is asserted (if enabled).
NOTE:
Inconsistency of Desynchronization Flag in Compatibility Mode MibSPI
Because of the nature of this error, under some circumstances it is possible for a desync
error detected for the previous buffer to be visible in the current buffer. This is due to the fact
that receive completion flag/interrupt will be generated when the buffer transfer is completed.
But desync will be detected after the buffer transfer is completed. So, if VBUS master reads
the received data quickly when an RXINT is detected, then the status flag may not reflect the
correct desynchronization condition. This inconsistency in the desync flag is valid only in
compatibility mode of MibSPI. In multi-buffer mode, the desync flag is always assured to be
for the current buffer.
