Introduction
117
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
Table 2-1. Definition of Terms (continued)
Acronym/Term
Full Form
Description
HTUx
High-end timer Transfer Unit
The HTU is a dedicated transfer unit for the New Enhanced High-End Timer
module. The HTU has a native interface to the N2HET RAM, and is used to
transfer data to / from the N2HET RAM from / to another region in the device
memory-map. There is one HTU per N2HET module, so that there are 2 HTU
modules on the device. The HTUx are bus masters in this device.
I2Cx
Inter-Integrated Circuit
controller
The I2C module is a multi-master communication module providing an interface
between the device and an I2C-compatible device via the I2C serial bus. The
I2C supports both 100 Kbps and 400 Kbps speeds.
IOMM
IO Multiplexing Module
This module controls the multiplexing on the device I/Os. Multiple functions can
be multiplexed onto the same device IO. Through IOMM module, user can
enable a specific function onto a device pin.
LINx
Local Interconnect Network
controller
The LIN module supports the Local Interconnect standard revision 2.1 and can
be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format.
Lockstep
–
This is the mode of operation of the dual ARM Cortex-R5F CPUs. The outputs of
the two CPUs are compared on each CPU clock cycle. Any miscompare is
flagged as an error of the highest severity level. In addition to the lockstep
CPUs, the two Vector Interrupt Module (VIM) are also in lockstep.
MibSPIx
Multi-Buffered Serial
Peripheral Interface
The MibSPIx modules also support the standard SPI communication protocol.
The transfers are all grouped into transfer chunks called “transfer groups”. These
transfer groups are made up of one ore more buffers in the MibSPIx RAM. The
RAM is used to hold the control information and data to be transmitted, as well
as the status information and data that is received. There are five MibSPI
modules in this device.
N2HETx
New Enhanced High-End
Timer
The N2HET is an advanced intelligent timer that provides sophisticated timing
functions for real-time applications. The timer is software-controlled, using a
reduced instruction set, with a specialized timer micromachine and an attached
I/O port. The N2HET can be used for pulse width modulated outputs, capture or
compare inputs, or general-purpose I/O.
NMPUx
Enhanced Memory Protection
Unit
There are three standalone NMPUs on this device protecting memory
transactions initiated by DMA, EMAC and other masters onto the resources on
the device. In this device, all transactions initiated by non-CPU masters will go
through two levels of MPU protection. The two levels can be a combination of
two NMPU in series or one standalone NMPU and one build-in MPU as part of
the master. One NMPU is dedicated to the DMA port connecting to the CPU
Interconnect Subsystem as the second level protection while the built-in MPU
inside the DMA acts as the first level protection. HTUx and FTU all have their
built-in MPU acting as the first level protection. All accesses initiated by the
masters on the Peripheral Interconnect Subsystem side will funnel through
another NMPU sitting in between the path connecting the Peripheral
Interconnect Subsystem to the CPU Interconnect Subsystem. This will act as the
second level protection for HTUx, FTU and EMAC. EMAC does not have the
built-in MPU and hence a standalone NMPU is instantiated between the EMAC
and the interconnect.
Peripheral
Interconnect
Subsystem
Peripheral Side Switched
Central Resource Controller
This is one of the two main SCRs in the device. It arbitrates between the
accesses from multiple bus masters to the bus slaves using a round robin
priority scheme.
PCRx
Peripheral Central Resource
controller
The PCR manages the accesses to the peripheral registers and peripheral
memories. It provides a global reset for all the peripherals. It also supports the
capability to selectively enable or disable the clock for each peripheral
individually. The PCR also manages the accesses to the system module
registers required to configure the device’s clocks, interrupts, and so on. The
system module registers also include status flags for indicating exception
conditions – resets, aborts, errors, interrupts. This device has three PCR
modules with each capable to access different peripherals as shown in the block
diagram. The three PCRs are slaves to the Peripheral Interconnect Subsystem.
PMM
Power Management Module
This module controls the clock gating to the various logic power domains in the
device. Through PMM, user can place a power domain among Active, Idle or Off
modes. This device does not implement physical power domains in which power
can be turned off. Trying to turn off a power domain has no effect on this device
in terms of power consumption but clocks will be gated off to remove dynamic
power. Idle and Off modes in this device behave the same from power
consumption perspective.
