Texas Instruments TMS570LC4357, Technical Reference Manual

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0 2 1 0
0 1 01 01 01 01 01 01
VCLK2
HR Clock
LR Clock
Instruction
LR Counter
Pin HET[0]
Z-Flag
LRP
HRP
25-bit ECMP
match
Pin action in next
loop resolution cycle
+
high resolution delay
CNT resets
Sets Z-Flag
Opposite Pin action in
next loop resolution
cycle
4 0 1 2 3 4 0 1
HR Counter
HR delay
N2HET Functional Description
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980 SPNU563A – March 2018
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High-End Timer (N2HET) Module
When the 25-bit (loop resolution) compare matches, the HR compare value will be loaded from the 7 lower
bits of the instruction data field to the HR counter. At the next loop resolution clock, the HR counter will
count down at the HR clock frequency and perform the pin action when it reaches zero.
In the example illustrated by Figure 23-19 , the 25-bit compare value is 1 and the 7-bit HR compare value
is 2. According to Section 23.2.3.2 , depending on the loop resolution divide rate (lr), only certain bits of the
7-bit HR compare value are valid. In this example only the upper 2 bits (D[6:5]) are taken into account.
The example program below has a setting of hr_data = 100000b. Shifting this value right by 5 bits, results
in 10b which equals the two HR clock cycles delay mentioned above.
Figure 23-19. ECMP Execution Timings
HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00 CNT { next= L01, reg=A, irq=OFF, max = 4 }
L01 ECMP { next= L00, cond_addr= L00, hr_lr=HIGH, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x40 }
; 25 bit compare value is 1 and the 7-bit HR compare value is 2
; (Because of lr=4 the D[4:0] of the 7-bit HR field are ignored )
NOTE: ECMP Opposite Actions
ECMP opposite pin actions are always synchronized to the loop resolution clock.
Changing the duty cycle of a PWM generated by an ECMP instruction, can lead to a missing pulse if the
data field of the instruction is updated directly. This can happen when it is changed from a high value to a
lower value while the CNT instruction has already passed the new updated lower value. To avoid this a
synchronous duty cycle update can be performed with the use of an additional instruction (MOV32). This
instruction is only executed when the compare of the ECMP matches. For this the cond_addr of the ECMP
needs to point to the MOV32. On execution of the MOV32, it moves its data field into the data field of the
ECMP. The update of the duty cycle has to be made to the MOV32 data field instead of the ECMP data
field.