Module Operation
2110
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Data Modification Module (DMM)
36.2 Module Operation
The DMM receives data over the DMM pins from external systems and writes the received data directly to
the base address programmed in the module plus offset address given in the packet or into a buffer
specified by start address and length. It leverages the protocol defined by the RAM Trace Port (RTP)
module to have a common interface definition for external systems. It can also be used to connect an RTP
and DMM module together for fast processor intercommunication.
The DMM module provides two modes of operation:
•
Trace Mode:
In this mode, the DMM writes the received data directly to an address that is calculated
from the base address programmed into the destination register (
plus the offset address contained in the received packet. An interrupt can be generated when data is
written the lowest address of a programmed region. This capability enables the sender to raise an
interrupt at the receiver while sending specific information.
•
Direct Data Mode:
In this mode, the DMM writes the received data into an address range of the 4GB
address space. The buffer start address (
) and blocksize (
) is
programmable in the DMM module. When the buffer reaches its end address, the buffer pointer wraps
around and points to the beginning of the buffer again. The EO_BUFF flag (
) will be set
and if enabled, an interrupt will be generated to indicate a buffer-full condition. Another interrupt, can
be configured to indicate different buffer fill levels. This can be accomplished by programming a certain
fill level into the DMMINTPT register (
). The PROG_BUFF flag (
)
indicates that this level has been reached.
Data will be captured by the input buffer and moved to the appropriate bit field in the deseralizer. When
the deseralizer is completely full, the data will be moved to the output buffer register. A two-level buffer is
implemented to avoid overflow conditions if the internal bus is occupied by other transactions. In addition
the DMMENA signal can be used to signal the external hardware that an overflow might occur if more
data is sent. The automatic generation of the DMMENA signal can be configured by setting the ENAFUNC
bit (
). While the DMMENA signal is active, the DMM module will not receive any new data.
The DMM is a bus master and forwards the received data to the bus system. The write operation will be
minimally intrusive to the program flow, because the CPU/DMA access will only be blocked if the
CPU/DMA accesses the same resource as the DMM.
To prevent an external system from overwriting critical data in the memory while configured in Trace
Mode, a memory protection mechanism is implemented via a programmable start address and block size
of a region. A maximum of four destinations with two regions each are supported.
For proper operation, at least DMMCLK, DMMSYNC and DMMDATA[0] need to be programmed in
functional mode (
). If a large amount of data should be transmitted in a short time, more
data pins should be used in functional mode. The module supports 1, 2, 4, 8, or 16-pin configurations.
The module can be configured to handle a free running clock provided on DMMCLK (
).
Clock pulses between two DMMSYNC pulses that exceed the number of valid clock pulses for a packet
will be ignored.
36.2.1 Data Format
Below is a description of the packet and frame format.
36.2.1.1 Clocking Scheme
The DMM supports both continuous and noncontinuous clocking. The clock received on DMMCLK in the
continuous clocking scheme is a free-running clock. In noncontinuous clocking scheme, the clock will stop
after each packet and will start with the reception of a DMMSYNC signal.
36.2.1.2 Trace Mode Packet
illustrates the trace mode packet format. One packet consists of 2 bits (DEST) denoting the
destination in which the data is stored, 2 status bits (STAT), the 2-bit SIZE of the data, the 18-bit address
of where the data should be written to, and a variable data field.
