EMIF Module Architecture
816
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
21.2.6.4.2 Asynchronous Write Operations (Normal Mode)
NOTE:
During an entire asynchronous write operation, the EMIF_nOE pin is driven high.
An asynchronous write is performed when any of the requesters mentioned in
request a
write to memory in the asynchronous bank of the EMIF. After the request is received, a write operation is
initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
. In the event that the write request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous write operation in Normal Mode are described in
. Also,
shows an example timing diagram of a basic write operation.
Table 21-20. Asynchronous Write Operation in Normal Mode
Time Interval
Pin Activity in Normal Mode
Turnaround
period
Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous
n
configuration register (CE
n
CFG). There are two exceptions
to this rule:
• If the current write operation was directly proceeded by another write operation, no turn-around cycles are
inserted.
• If the current write operation was directly proceeded by a read operation and the TA field has been cleared
to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turn-around cycles to complete, it again checks to make sure that the write
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in CE
n
CFG.
• The address pins EMIF_A and EMIF_BA and the data pins EMIF_D become valid. The EMIF_A and
EMIF_BA pins carry the values described in
• EMIF_nCS[4:2] falls to enable the external device (if not already low from a previous operation).
Strobe period
The following actions occur at the start of the strobe period of a write operation:
1.
EMIF_nWE falls
2.
The EMIF_nDQM pins become valid as byte enables.
The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period:
1.
EMIF_nWE rises
2.
The EMIF_nDQM pins deactivate
In
, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to accept the data.
contains more details on using the
EMIF_nWAIT pin.
End of the hold
period
At the end of the hold period:
• The address pins EMIF_A and EMIF_BA become invalid
• The data pins become invalid
• EMIF_nCS[n] (n = 2, 3, or 4) rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
