Low Power Oscillator and Clock Detect (LPOCLKDET)
523
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
The automatic switch-over from oscillator to HF LPO allows the application to execute at a reduced
frequency and respond to a problem with the external crystal/resonator. During and after an oscillator
failure, the oscillator CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT), of the System
and Peripheral Control Registers, is set along with the OSCFAIL flag in the Global Status Register
(GLBSTAT), of the System and Peripheral Control Registers.
It is useful to explicitly change the GHVSRC register, defining the current clock source for
GCLK1/HCLK/VCLK domains, to the HF LPO after an oscillator failure.
When reset on oscillator failure is set, PLLCTL1.23 (ROF), the device responds to an oscillator failure by
generating a device reset.
14.4.3 Recovery from Oscillator Failure
If the oscillator fails, the clock detect switches the HF LPO frequency onto the oscillator source into the
GCM. The OSCFAIL flag in the Global Status Register (GLBSTAT) of the System and Peripheral Control
Registers is also set.
The oscillator may be re-enabled (though if the failure was caused by a hard-fault, the re-enable will fail)
through the following procedure:
1. Switch all clock domains from the oscillator to the HF LPO (for example, GHVSRC uses HF LPO,
VCLKAn uses HF LPO or VCLK, and so on).
2. If the PLL is used, disable the PLL by setting the appropriate bit in the Clock Source Disable Set
Register (CSDISSET) of the System and Peripheral Control Registers.
3. Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register
(CSDISSET). This action resets the clock detect and allows the oscillator to propagate through GCM
clock source 0.
4. Re-enable the oscillator by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR) of the System and Peripheral Control Registers.
5. Clear the OSCFAIL flag in the Global Status Register (GLBSTAT) by writing a 1 to the bit. The PLL slip
bits may also be set on an oscillator failure. These can also be cleared.
6. Switch the clock domains back to the oscillator.
7. Re-enable the PLL by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR).
NOTE:
Clock Re-Enable Procedure Will Fail If Caused by a Hard Failure
Although it is possible to re-enable the oscillator after a failure, if the oscillator failure was
caused by a hard fault (for example, disconnected crystal/resonator terminal), the re-enable
process will fail.
14.4.4 LPOCLKDET Enable
The LPO is enabled by default while nPORRST is low. During this time, the current source initializes,
holding the relaxation oscillator in reset until initialized. After the current source releases the HF LPO and
the LF LPO, these clock frequencies slew to their final frequencies; the final frequency may be achieved
while nPORRST is active or after its release. After, nPORRST is released, the HF LPO Valid signal is set
32 HF LPO clock cycles later.
The clock detect is enabled once the oscillator and HF LPO are valid. Because an oscillator failure could
occur from reset, the clock detect logic must provide an override path. If the HF LPO is valid and the
oscillator is not valid, the clock detect circuitry will become active (overriding the oscillator invalid signal)
after 16K LF LPO cycles (about 200 ms).
