Module Operation
1245
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
The received message is stored only if the cycle counter value of the cycle during which the message is
received matches an element of the receive buffer’s cycle set. Other filter criteria must also be met.
The content of a transmit buffer is transmitted on the configured channel(s) when an element of the cycle
set matches the current cycle counter value. Other filter criteria must also be met.
26.2.8.3 Channel ID Filtering
There is a 2-bit channel filtering field (CHA, CHB) located in the header section of each message buffer in
the message RAM. It serves as a filter for receive buffers, and as a control field for transmit buffers (see
).
Table 26-10. Channel Filtering Configuration
CHA
CHB
Transmit Buffer
Receive Buffer
Transmit frame
Store valid receive frame
1
1
On both channels (static segment only)
Received on channel A or B (store first semantically
valid frame, static segment only)
1
0
On channel A
Received on channel A
0
1
On channel B
Received on channel B
0
0
No transmission
Ignore frame
The contents of a transmit buffer is transmitted on the channels specified in the channel filtering field when
the slot counter filtering and cycle counter filtering criteria are also met. Only in static segment a transmit
buffer may be set up for transmission on both channels (CHA and CHB set).
Valid received frames are stored if they are received on the channels specified in the channel filtering field
when the slot counter filtering and cycle counter filtering criteria are also met. Only in static segment a
receive buffer may be setup for reception on both channels (CHA and CHB set).
NOTE:
If a message buffer is configured for the dynamic segment and both bits of the channel
filtering field are set to 1, no frames are transmitted and received frames are ignored (same
function as CHA = CHB = 0)
26.2.8.4 FIFO Filtering
For FIFO filtering there is one rejection filter and one rejection filter mask available. The FIFO filter
consists of channel filter FRF.CH(1-0), frame ID filter FRF.FID(10-0), and cycle counter filter FRF.CYF(6-
0). Registers FRF and FRFM can be configured in DEFAULT_CONFIG or CONFIG state only. The filter
configuration in the header section of message buffers belonging to the FIFO is ignored.
The 7-bit cycle counter filter determines the cycle set to which frame ID and channel rejection filter are
applied. In cycles not belonging to the cycle set specified by FRF.CYF(6-0), all frames are rejected.
A valid received frame is stored in the FIFO if channel ID, frame ID, and cycle counter are not rejected by
the configured rejection filter and rejection filter mask, and if there is no matching dedicated receive buffer.
