FlexRay Module Registers
1293
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
26.3.1.15 TCR Single-Bit Error Status (TSBESTAT)
After an ECC single-bit error in the Transfer Configuration RAM (TCR) occurred, the SE flag is set and the
affected address is stored in this register. The register is updated without regard to the ECC single-bit
error correction activation in the ECC Control Register (ECC_CTRL).
The contents of this register is cleared automatically when reading the register.
NOTE:
ECC single-bit error can only be indicated by the SE bit when ADR is cleared. Since the
contents of ADR is undefined after reset, it is recommended to clear the register by reading
it.
Figure 26-53. TCR Single-Bit Error Status (TSBESTAT) [offset_TU = 6Ch]
31
30
16
SE
Reserved
R-0
R-0
15
9
8
0
Reserved
ADR
R-0
RC-U
LEGEND: R = Read only; RC = Clear on read; U = value is undefined; -
n
= value after reset
Table 26-33. TCR Single-Bit Error Status (TSBESTAT) Field Descriptions
Bit
Field
Value
Description
31
SE
ECC Single-Bit Error. The flag signals an ECC single-bit error to the host. The flag is set when an
ECC single-bit error in TCR is detected. The flag is set without regard to the single-bit error lock
setting of ECC Control Register (ECC_CTRL).
ECC multi-bit errors are indicated by a separate PE bit in the Transfer Error Interrupt Flag (TEIF)
register.
0
No ECC single-bit error occurred.
1
ECC single-bit error occurred.
30-9
Reserved
0
Reads return 0. Writes have no effect.
8-0
ADR
Address of failing TCR word location. ADR[8-2] is the TCR word address where the ECC single-bit
error occurred. ADR[1-0] are always driven as 00.