Overview
461
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
System Memory Protection Unit (NMPU)
11.1 Overview
The System Memory Protection Unit module(s) provide an mechanism to control the memory access
rights of bus masters in the system other than the host CPU. The programmer's model for the System
Memory Protection unit is similar to but a subset of the host CPU's own memory protection unit. It allows
memory partition into multiple regions and allows individual access protection for each region from a bus
master point of view. An access from bus master is checked against each memory region access
permission to make sure that the access from bus master does not alter the unintended memory region
that could cause a system failure.
11.1.1 Features
NMPU offers the following main features:
•
Software programmer model is similar to but a subset of the host CPUs own memory protection unit.
•
Provide protection to memory regions ranging from 32-bytes to 4GB in size
•
Up to 8 memory protection regions. Note that the number of memory region is different for each bus
master IP that the NMPU is dedicated for. Each region is defined by the base address and region size
that are programmable in NMPU control registers.
defines the number of region available
for the corresponding bus master IP.
•
Programmable access permissions for each region such as full access, read-only, write-only, and no
access.
•
Different access permissions for user and privilege mode.
•
On access violation, NMPU can notify ESM if ERRENA key in MPUCTRL1 register (
) is
enabled.
Table 11-1. NMPU Region
NMPU Module
Number of Available Regions
DMA-NMPU
8
Peripheral Interconnect Subsystem-NMPU
8
EMAC-NMPU
2
11.1.2 Safety Diagnostic
NMPU offers the following safety diagnostic capabilities:
•
Provide a lock mechanism to avoid unintentional changes to NMPU control registers.
•
Provide diagnostic capability to check the MPU region access permission logic.