DCAN Control Registers
1456
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Controller Area Network (DCAN) Module
27.17.1 CAN Control Register (DCAN CTL)
NOTE:
The Bus-Off recovery sequence (see CAN specification) cannot be shortened by setting or
resetting Init bit. If the module goes Bus-Off, it will automatically set the Init bit and stop all
bus activities.
When the Init bit is cleared by the application again, the module will then wait for 129
occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal
operation. At the end of the Bus-Off recovery sequence, the error counters will be reset.
After the Init bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0
error code is written to the Error and Status Register, enabling the CPU to check whether the
CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the
Bus-Off recovery sequence.
Figure 27-20. CAN Control Register (DCAN CTL) [offset = 00h]
31
26
25
24
Reserved
WUBA
PDR
R-0
R/W-0
R/W-0
23
21
20
19
18
17
16
Reserved
DE3
DE2
DE1
IE1
InitDbg
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
15
14
13
10
9
8
SWR
Reserved
PMD
ABO
IDS
R/WP-0
R-0
R/W-5h
R/W-0
R/W-0
7
6
5
4
3
2
1
0
Test
CCE
DAR
Reserved
EIE
SIE
IE0
Init
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write protected by Init bit; -
n
= value after reset
Table 27-7. CAN Control Register (DCAN CTL) Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
These bits are always read as 0. Writes have no effect.
25
WUBA
Automatic wake up on bus activity when in local power down mode.
0
No detection of a dominant CAN bus level while in local power down mode.
1
Detection of a dominant CAN bus level while in local power down mode is enabled. On
occurrence of a dominant CAN bus level, the wake up sequence is started. (Additional
information can be found in
Note:
The CAN message, which Initiates the bus activity, cannot be received. This means that
the first message received in power down and automatic wake-up mode, will be lost.
24
PDR
Request for local low power down mode.
0
No application request for local low power down mode. If the application has cleared this bit
while DCAN in local power down mode, also the Init bit has to be cleared.
1
Local power down mode has been requested by application. The DCAN will acknowledge the
local power down mode by setting bit PDA in Error and Status Register. The local clocks will be
turned off by DCAN internal logic (Additional information can be found in
23-21
Reserved
0
These bits are always read as 0. Writes have no effect.
20
DE3
Enable DMA request line for IF3.
0
Disabled
1
Enabled
Note:
A pending DMA request for IF3 remains active until first access to one of the IF3
registers.