Introduction
1996
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Enhanced Pulse Width Modulator (ePWM) Module
35.1 Introduction
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources that can operate together as required to form a system. This modular approach results in an
orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to
understand its operation quickly.
In this document the letter x within a signal or module name is used to indicate a generic ePWM instance
on a device. For example output signals EPWMxA and EPWMxB refer to the output signals from the
ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B
belong to ePWM4.
35.1.1 Submodule Overview
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA
and EPWMxB. Multiple ePWM modules are instanced within a device as shown in
. Each
ePWM instance is identical and is indicated by a numerical value starting with 1. For example, ePWM1 is
the first instance and ePWM3 is the third instance in the system, and ePWMx indicates any instance.
The ePWM modules are chained together via a clock synchronization scheme that allows them to operate
as a single system when required. Additionally, this synchronization scheme can be extended to the
capture peripheral modules (eCAP). Modules can also operate stand-alone.
Each ePWM module supports the following features:
•
Dedicated 16-bit time-base counter with period and frequency control
•
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
–
Two independent PWM outputs with single-edge operation
–
Two independent PWM outputs with dual-edge symmetric operation
–
One independent PWM output with dual-edge asymmetric operation
•
Asynchronous override control of PWM signals through software.
•
Programmable phase-control support for lag or lead operation relative to other ePWM modules.
•
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
•
Dead-band generation with independent rising and falling edge delay control.
•
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
•
A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
•
All events can trigger both CPU interrupts and ADC start of conversion (SOC)
•
Programmable event prescaling minimizes CPU overhead on interrupts.
•
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM module is connected to the input/output signals shown in
. The signals are
described in detail in subsequent sections.
Each ePWM module consists of eight submodules and is connected within a system via the signals shown
in
.
