Architecture
1829
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
EMAC/MDIO Module
32.2.8.1.1 MDIO Clock Generator
The MDIO clock generator controls the MDIO clock based on a divide-down of the VCLK3 peripheral clock
in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHz, although typical operation
would be 1.0 MHz. Since the VCLK3 peripheral clock frequency is configurable, the application software
or driver controls the divide-down amount. See the device datasheet for peripheral clock speed
specifications.
32.2.8.1.2 Global PHY Detection and Link State Monitoring
The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in the
system. The module tracks whether or not a PHY on a particular address has responded, and whether or
not the PHY currently has a link. Using this information allows the software application to quickly
determine which MDIO address the PHY is using.
32.2.8.1.3 Active PHY Monitoring
Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link state
by reading the MDIO PHY link status register (LINK). Link change events are stored on the MDIO device
and can optionally interrupt the CPU. This allows the system to poll the link status of the PHY device
without continuously performing costly MDIO accesses.
32.2.8.1.4 PHY Register User Access
When the CPU must access MDIO for configuration and negotiation, the PHY access module performs
the actual MDIO read or write operation independent of the CPU. This allows the CPU to poll for
completion or receive an interrupt when the read or write operation has been performed. The user access
registers USERACCESS
n
allows the software to submit the access requests for the PHY connected to the
device.
