Control Registers
1563
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-28. SPI Delay Register (SPIDELAY) Field Descriptions (continued)
Bit
Field
Value
Description
23-16
T2CDELAY
0-FFh
Transmit-end-to-chip-select-inactive-delay. See
for an example. T2CDELAY is used
only in master mode. It defines a hold time for the slave device that delays the chip select
deactivation by a multiple of VCLK cycles after the last bit is transferred. The hold time value is
calculated as follows:
t
T2CDELAY
= (T21) × VCLK Period
Example: VCLK = 25 MHz -> VCLK Period = 40ns; T2CDELAY = 03h;
> t
T2CDELAY
= 160 ns
After the last data bit (or parity bit) is being transferred the chip select signal is held active for 160
ns.
Note: If phase = 0, then between the last edge of SPICLK and rise-edge of SPICS there will
be an additional delay of 0.5 SPICLK period. This is as per the SPI protocol.
Both C2TDELAY and T2CDELAY counters do not have any dependency on the SPIENA pin
value. Even if the SPIENA pin is asserted by the slave, the master will continue to delay the start
of SPICLK until the C2TDELAY counter overflows.
Similarly, even if the SPIENA pin is deasserted by the slave, the master will continue to hold the
SPICS pins active until the T2CDELAY counter overflows. In this way, it is guaranteed that the
setup and hold times of the SPICS pins are determined by the delay timers alone. To achieve
better throughput, it should be ensured that these two timers are kept at the minimum possible
values.
15-8
T2EDELAY
0-FFh
Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. It
defines a time-out value as a multiple of SPI clock before SPIENA signal has to become inactive
and after SPICS becomes inactive. SPICLK depends on which data format is selected. If the slave
device is missing one or more clock edges, it becomes de-synchronized. In this case, although the
master has finished the data transfer, the slave is still waiting for the missed clock pulses and the
ENA signal is not disabled.
The T2EDELAY defines a time-out value that triggers the DESYNC flag, if the SPIENA signal is
not deactivated in time. The DESYNC flag is set to indicate that the slave device did not de-assert
its SPIENA pin in time to acknowledge that it received all bits of the sent word. See
for an example of this condition.
Note: DESYNC is also set if the SPI detects a de-assertion of SPIENA before the end of the
transmission. The time-out value is calculated as follows:
t
T2EDELAY
= T2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; T2EDELAY = 10h;
> t
T2EDELAY
= 2 µs
The slave device has to disable the ENA signal within 2, otherwise DESYNC is set and an
interrupt is asserted (if enabled).
7-0
C2EDELAY
0-FFh
Chip-select-active to ENA-signal-active time-out. C2EDELAY is used only in master mode and it
applies only if the addressed slave generates an ENA signal as a hardware handshake response.
C2EDELAY defines the maximum time between when the SPI activates the chip-select signal and
the addressed slave has to respond by activating the ENA signal. C2EDELAY defines a time-out
value as a multiple of SPI clocks. The SPI clock depends on whether data format 0 or data format
1 is selected. See
for an example of this condition.
Note: If the slave device does not respond with the ENA signal before the time-out value is
reached, the TIMEOUT flag in the SPIFLG register is set and a interrupt is asserted (if
enabled).
If a time-out occurs, the SPI clears the transmit request of the timed-out buffer, sets the TIMEOUT
flag for the current buffer, and continues with the transfer of the next buffer in the sequence that is
enabled.
The timeout value is calculated as follows: t
C2EDELAY
= C2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; C2EDELAY = 30 h;
> t
C2EDELAY
= 6 ms
The slave device has to activate the ENA signal within 6 ms after the SPI has activated the chip
select signal (SPICS), otherwise the TIMEOUT flag is set and an interrupt is asserted (if enabled).
