How to Use EPC
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SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Error Profiling Controller (EPC)
12.3 How to Use EPC
12.3.1 Functional Mode
Following steps are the recommended sequences to initialize EPC:
1. Set up correct values for SERRENA and CAMFIFO FULL ENA bits in EPCCNTRL. Setting SERRENA
will enable correctable error event generation to ESM. Setting CAMFIFO FULL ENA will enable CAM
full or FIFO full interrupt to the CPU. You need to set these values in according to their safety
application requirement.
2. Read CAMAVAILSTAT to ensure that all CAM indexes are available after system reset.
On CAM or FIFO full interrupt, following sequences are recommended to query the EPC:
1. Read EPCERRSTAT and FIFOFULLSTAT to determine if this is CAM or FIFO full.
a. If it is FIFO full, the FIFOFULLSTAT indicates which IP FIFO is full so you can make a decision on
whether to put the system in safe state if the particular IP happens to be a critical IP in safety
application or doing extra diagnostic of the corresponding IP RAM during diagnostic time. Clear the
FIFO full by write clear to the FIFOFULLSTAT register.
b. If it is CAM full, you need to read CAM content to find out if most of the correctable fault happens
to be in the same IP or scatter among IP in order to take decision on whether to put the system in
safe state or decides to run certain RAM test during diagnostic time. You can also keep track of
the correctable fault in system RAM in order to clear the CAM index to avoid CAM overflow
condition.
On correctable error event or CAM overflow or FIFO overflow from ESM interrupt CPU, following
sequences are recommended to query the EPC:
1. Read EPCERRSTAT and OVRFLWSTAT registers to determine if this is CAM or FIFO overflow or a
registration of new correctable fault event in CAM.
a. If it is FIFO overflow, the OVRFLWSTAT indicates which IP FIFO has overflow so you can make
decision on whether to put the system in safe state if the particular IP happens to be a critical IP in
safety application or doing extra diagnostic of the corresponding IP RAM during diagnostic time.
Clear the FIFO overflow by write clear to the OVRFLWSTAT register.
b. If it is CAM overflow, that means you do not service the CAM full interrupt in time. You need to
read CAM content to find out if most of the correctable fault happens to be in the same IP or
scatter among IP in order to take decision on whether to put the system in safe state or decides to
run certain RAM test during diagnostic time. You can also keep track of the correctable fault in
system RAM in order to clear the CAM index to avoid CAM overflow condition.
c. If it is none of the two above cases, then it is a new correctable fault event register on CAM. You
can read the CAM index registers and CAM content registers to determine which IP RAM or RAM
location that has the correctable fault and does a quick diagnose of that RAM location by backing
up location content, write and read back new RAM value. If it is a transient fault, restores RAM
backup data and clear the CAM index. Otherwise, mark it as permanent fault by not clearing the
index to available so that it does not generate correctable error event again.
On uncorrectable error event, following sequences are recommended to query the EPC:
1. Read UERRSTAT register to determine which IP_(n) causing uncorrectable fault.
2. Read the corresponding UERR_ADDR_(n) to determine the location of the fault.
3. Diagnose the corresponding location to determine if this is a permanent or transient fault. Depending
on the criticality of this uncorrectable fault in safety application, it is up to you to bring the system to
safe state or not.
