Clocks
146
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.4.3.1
Typical Software Sequence to Enter a Low-Power Mode
1. Disable all non-CPU bus masters so they do not carry out any further bus transactions.
2. Program the flash banks and flash pump fall-back modes to be “sleep”.
The flash pump transitions from active to sleep mode only after all the flash banks have switched from
active to sleep mode.
3. Disable the clock sources that are not required to be kept active.
A clock source does not get disabled until all clock domains using that clock source are disabled first,
or are configured to use an alternate clock source.
4. Disable the clock domains that are not required to be kept active.
A clock domain does not get disabled until all modules using that clock domain “give their permission”
for that clock domain to be turned off.
5. Idle the Cortex-R5F core.
The ARM Cortex-R5F CPU has internal power management logic, and requires a dedicated instruction
to be used in order to enter a low power mode. This is the Wait For Interrupt (WFI) instruction.
When a WFI instruction is executed, the Cortex-R5F core flushes its pipeline, flushes all write buffers,
and completes all pending bus transactions. At this time the core indicates to the system that the clock
to the core can be stopped. This indication is used by the Global Clock Module (GCM) to turn off the
CPU clock domain (GCLK1) if the CDDIS register bit 0 is set.
2.4.3.2
Special Considerations for Entry to Low Power Modes
Some bus master modules – DMA, High-End Timer Transfer Units (HTUx), FlexRay Transfer Unit (FTU),
and Parameter Overlay Module (POM), can have ongoing transactions when the application wants to
enter a low power mode to turn off the clocks to those modules. This is not recommended as it could
leave the device in an unpredictable state. Refer to the individual module user guides for more information
about the sequence to be followed to safely enter a low-power mode.
2.4.3.3
Selecting Clock Source Upon Wake Up
The domains for CPU clock (GCLK1), the system clock (HCLK) and the peripheral clock (VCLKx) use the
same clock source selected via the GHVSRC field of the GHVSRC register. The GHVSRC register also
allows the application to choose the clock source after wake up via the GHVWAKE field.
When a wake up condition is detected, if the selected wake up clock source is not already active, the
global clock module (GCM) will enable this selected clock source, wait for it to become valid, and then use
it for the GCLK1, HCLK, and VCLKx domains. The other clock domains VCLKAx and RTICLK1 retain the
configuration for their clock source selection registers – VCLKASRC, VCLKACON1 and RCLKSRC.
2.4.4 Clock Test Mode
The TMS570LC43x microcontrollers support a test mode which allows a user to bring out several different
clock sources and clock domains on to the ECLK1 terminal in addition to outputting the external clock.
This is very useful information for debug purposes. Each clock source also has a corresponding clock
source valid status flag in the Clock Source Valid Status (CSVSTAT) register. The clock source valid
status flags can also be brought out on to the N2HET1[12] terminal in this clock test mode.
The clock test mode is controlled by the CLKTEST register in the system module register frame (see
The clock test mode is enabled by writing 0x5 to the CLK_TEST_EN field.
