ePWM Submodules
2046
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Enhanced Pulse Width Modulator (ePWM) Module
shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD])
bits specify the number of events required to cause an interrupt pulse to be generated. The choices
available are:
•
Do not generate an interrupt.
•
Generate an interrupt on every event
•
Generate an interrupt on every second event
•
Generate an interrupt on every third event
Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) bits. The
event can be one of the following:
•
Time-base counter equal to zero (TBCTR = 0x0000).
•
Time-base counter equal to period (TBCTR = TBPRD).
•
Time-base counter equal to zero or period (TBCTR = 0x0000 || TBCTR = TBPRD)
•
Time-base counter equal to the compare A register (CMPA) when the timer is incrementing.
•
Time-base counter equal to the compare A register (CMPA) when the timer is decrementing.
•
Time-base counter equal to the compare B register (CMPB) when the timer is incrementing.
•
Time-base counter equal to the compare B register (CMPB) when the timer is decrementing.
The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT])
register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they
reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops
counting and its output is set. The counter is only cleared when an interrupt is sent to the VIM.
When ETPS[INTCNT] reaches ETPS[INTPRD] the following behaviors will occur:
•
If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
•
If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
•
If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be
reset (so no interrupts are generated). Writing a 1 to the ETFRC[INT] bit will increment the event counter
INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the
counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored.
The above definition means that you can generate an interrupt on every event, on every second event, or
on every third event. An interrupt cannot be generated on every fourth or more events.
