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Texas Instruments TMS570LC4357, Technical Reference Manual

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RTP Control Registers

2173

SPNU563A – March 2018

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Copyright © 2018, Texas Instruments Incorporated

RAM Trace Port (RTP)

37.3.6 RTP RAM 3 Trace Region Registers (RTPRAM3REG[1:2])

FIFO3 was originally designed to support RAM trace limiting to a maximum trace range of 256kB. In this
device, FIFO3 is dedicated for tracing the PCR1 peripheral accesses. Peripherals in PCR1 occupy a total
address range of 512kB of space. Therefore, it is not possible to trace the entire range of 512kB since
there are only 18 bits of address being traced out in the packet. You can use the two trace regions to
trace any two areas in the lower half of the PCR1's space from 0xFFF80000 to 0xFFFBFFFF provided
there is not an intentional or un-intentional access to the upper half of the space. If you want to trace the
upper half of PCR1's space from 0xFFFC0000 to 0xFFFFFFFF then the external hardware/software must
reconstruct the full 32-bit address by forcing address bit 18 high and also ensures that there is no
intentional or un-intentional accesses to the lower half of the space. Since the external hardware is unable
to distinguish between the lower half and the upper half of PCR1, you can not trace both of the halves at
the same time.

NOTE:

Bit REG (

Section 37.2.1.1

) in the protocol for peripheral trace will be not be applicable to the

PCR1 trace. PCR1 trace follows the RAM trace protocol with 18 bits of address trace out.

Figure 37-14

and

Table 37-15

illustrate these registers.

Figure 37-14. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) (offset = 1Ch and 20h)

31

29

28

27

24

23

18

17

16

CPU_DMA

RW

BLOCKSIZE

Reserved

STARTADDR

R/WP-0

R/WP-0

R/WP-0

R-0

R/WP-0

15

0

STARTADDR

R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -

n

= value after reset

Table 37-15. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) Field Descriptions

Bit

Field

Value

Description

31-29

CPU_DMA

When the device is configured in lock-step mode, bit 31 will return 0 and a write has no effect.
This bit field indicates if read or write operations are traced either coming from the CPU and/or
from the other master.

User and privilege mode read, privilege mode write:

0

Read or write operations are traced when coming from the CPU and the other master.

1h

Read or write operations are traced only when coming from the CPU.

2h

Read or write operations are traced only when coming from the other master.

3h

Reserved

28

RW

Read/Write. This bit indicates if read or write operations are traced in Trace Mode or Direct
Data Mode (read operation). If configured for write in Direct Data Mode (RTPGLBCTRL), the
data captured will be discarded. A write operation in Direct Data Mode has to be directly to the
RTP direct data mode write register (RTPDDMW) instead of to RAM. Depending on the
INV_RGN bit setting, accesses into or outside the region will be traced.

Read:

0

Read operations will be captured.

1

Write operations will be captured.

Write in Privilege:

0

Trace read accesses.

1

Trace write accesses.

Summary of Contents for TMS570LC4357

Page 1: ...TMS570LC43x 16 32 Bit RISC Flash Microcontroller Technical Reference Manual Literature Number SPNU563A March 2018...

Page 2: ...controllers 129 2 2 4 On Chip SRAM 134 2 3 Exceptions 139 2 3 1 Resets 139 2 3 2 Aborts 139 2 3 3 System Software Interrupts 141 2 4 Clocks 142 2 4 1 Clock Sources 142 2 4 2 Clock Domains 143 2 4 3 Lo...

Page 3: ..._STATUS 273 4 4 2 SDC Control Register SDC_CONTROL 274 4 4 3 Error Generic Parity Register ERR_GENERIC_PARITY 274 4 4 4 Error Unexpected Transaction Register ERR_UNEXPECTED_TRANS 275 4 4 5 Error Trans...

Page 4: ...ger Signal Generation from ePWMx Modules 315 6 5 6 Control for Generating Interrupt Upon External Fault Indication to N2HETx 318 6 5 7 Control for Synchronizing Time Bases for All ePWMx Modules 320 6...

Page 5: ...atus Register FEDAC_PBSTATUS 360 7 10 6 Flash Global Error and Status Register FEDAC_GBLSTATUS 361 7 10 7 Flash Error Detection and Correction Sector Disable Register FEDACSDIS 362 7 10 8 Primary Addr...

Page 6: ...2 L2RAMW Error Status Register RAMERRSTATUS 395 8 3 3 L2RAMW Diagnostic Data Vector High Register DIAG_DATA_VECTOR_H 398 8 3 4 L2RAMW Diagnostic Data Vector Low Register DIAG_DATA_VECTOR_L 398 8 3 5 L...

Page 7: ...ntrol Registers 446 10 8 1 STC Global Control Register 0 STCGCR0 447 10 8 2 STC Global Control Register 1 STCGCR1 448 10 8 3 Self Test Run Timeout Counter Preload Register STCTPR 449 10 8 4 STC Curren...

Page 8: ...Status Register UERRSTAT 491 12 4 4 EPC Error Status Register EPCERRSTAT 492 12 4 5 FIFO Full Status Register FIFOFULLSTAT 493 12 4 6 IP Interface FIFO Overflow Status Register OVRFLWSTAT 494 12 4 7 C...

Page 9: ...PLL BIST Control Register 3 SSWPLL3 537 14 7 Phase Locked Loop Theory of Operation 538 14 7 1 Phase Frequency Detector 538 14 7 2 Charge Pump and Loop Filter 539 14 7 3 Voltage Controlled Oscillator 5...

Page 10: ...574 16 4 16 ESM Status Shadow Register 2 ESMSSR2 574 16 4 17 ESM Influence ERROR Pin Set Status Register 4 ESMIEPSR4 575 16 4 18 ESM Influence ERROR Pin Clear Status Register 4 ESMIEPCR4 575 16 4 19...

Page 11: ...Register RTITBLCOMP 610 17 3 24 RTI Timebase High Compare Register RTITBHCOMP 610 17 3 25 RTI Set Interrupt Enable Register RTISETINTENA 611 17 3 26 RTI Clear Interrupt Enable Register RTICLEARINTENA...

Page 12: ...REGL1 654 18 4 17 Channel 1 CRC Value High Register CRC_REGH1 655 18 4 18 Channel 1 PSA Sector Signature Low Register PSA_SECSIGREGL1 655 18 4 19 Channel 1 PSA Sector Signature High Register PSA_SECSI...

Page 13: ...m Control Registers FIRQPR 0 3 686 19 9 10 Pending Interrupt Read Location Registers INTREQ 0 3 687 19 9 11 Interrupt Enable Set Registers REQENASET 0 3 688 19 9 12 Interrupt Enable Clear Registers RE...

Page 14: ...1 3 EMIF Registers 828 21 3 1 Module ID Register MIDR 828 21 3 2 Asynchronous Wait Cycle Configuration Register AWCC 829 21 3 3 SDRAM Configuration Register SDCR 830 21 3 4 SDRAM Refresh Control Regis...

Page 15: ...Results Memory Size Configuration Register ADBNDEND 914 22 3 25 ADC Event Group Sampling Time Configuration Register ADEVSAMP 915 22 3 26 ADC Group1 Sampling Time Configuration Register ADG1SAMP 915 2...

Page 16: ...ELMODECTRL 948 22 3 70 ADC Group1 Channel Selection Mode Control Register ADG1CHNSELMODECTRL 948 22 3 71 ADC Group2 Channel Selection Mode Control Register ADG2CHNSELMODECTRL 949 22 3 72 ADC Event Gro...

Page 17: ...dress Register HETPAR 1038 23 4 28 Parity Pin Register HETPPR 1039 23 4 29 Suppression Filter Preload Register HETSFPRLD 1040 23 4 30 Suppression Filter Enable Register HETSFENA 1040 23 4 31 Loop Back...

Page 18: ...ll Interrupt Enable Set Register HTU BFINTS 1156 24 4 10 Buffer Full Interrupt Enable Clear Register HTU BFINTC 1156 24 4 11 Interrupt Mapping Register HTU INTMAP 1157 24 4 12 Interrupt Offset Registe...

Page 19: ...R 1197 25 5 6 GIO Interrupt Flag Register GIOFLG 1200 25 5 7 GIO Offset Register 1 GIOOFF1 1201 25 5 8 GIO Offset B Register GIOOFF2 1202 25 5 9 GIO Emulation A Register GIOEMU1 1203 25 5 10 GIO Emula...

Page 20: ...entation in Debug Suspend Mode 1431 27 5 4 Message RAM Representation in Direct Access Mode 1431 27 5 5 ECC RAM 1432 27 6 Message Interface Register Sets 1433 27 6 1 Message Interface Register Sets 1...

Page 21: ...TL 1456 27 17 2 Error and Status Register DCAN ES 1459 27 17 3 Error Counter Register DCAN ERRC 1461 27 17 4 Bit Timing Register DCAN BTR 1462 27 17 5 Interrupt Register DCAN INT 1463 27 17 6 Test Reg...

Page 22: ...eral Purpose I O 1529 28 2 8 Low Power Mode 1529 28 2 9 Safety Features 1529 28 2 10 Test Features 1531 28 2 11 Module Configuration 1533 28 3 Control Registers 1535 28 3 1 SPI Global Control Register...

Page 23: ...1598 28 3 45 SPI Extended Prescale Register 2 EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3 1600 28 3 46 ECC Diagnostic Control Register ECCDIAG_CTRL 1601 28 3 47 ECC Diagnostic Status Register ECCDIAG_...

Page 24: ...7 13 SCI Data Buffers SCIED SCIRD SCITD 1698 29 7 14 SCI Pin I O Control Register 0 SCIPIO0 1699 29 7 15 SCI Pin I O Control Register 1 SCIPIO1 1700 29 7 16 SCI Pin I O Control Register 2 SCIPIO2 170...

Page 25: ...IFORMAT 1750 30 7 11 Baud Rate Selection Register BRS 1751 30 7 12 SCI Data Buffers SCIED SCIRD SCITD 1752 30 7 13 SCI Pin I O Control Register 0 SCIPIO0 1753 30 7 14 SCI Pin I O Control Register 1 SC...

Page 26: ...ock Control High Register I2CCKH 1787 31 6 6 I2C Data Count Register I2CCNT 1788 31 6 7 I2C Data Receive Register I2CDRR 1788 31 6 8 I2C Slave Address Register I2CSAR 1789 31 6 9 I2C Data Transmit Reg...

Page 27: ...isters C0MISCEN 1860 32 3 8 EMAC Control Module Receive Threshold Interrupt Status Registers C0RXTHRESHSTAT 1861 32 3 9 EMAC Control Module Receive Interrupt Status Registers C0RXSTAT 1862 32 3 10 EMA...

Page 28: ...AXLEN 1901 32 5 25 Receive Buffer Offset Register RXBUFFEROFFSET 1902 32 5 26 Receive Filter Low Priority Frame Threshold Register RXFILTERLOWTHRESH 1902 32 5 27 Receive Channel Flow Control Threshold...

Page 29: ...34 Enhanced Quadrature Encoder Pulse eQEP Module 1957 34 1 Introduction 1958 34 2 Basic Operation 1960 34 2 1 EQEP Inputs 1960 34 2 2 Functional Description 1961 34 2 3 eQEP Watchdog 1976 34 2 4 Unit...

Page 30: ...Converters 2063 35 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM 2065 35 3 7 Practical Applications Using Phase Control Between PWM Modules 2068 35 4 ePWM Registers 2070 35 4 1 Time...

Page 31: ...al Description 2161 37 2 6 Data Rate 2162 37 2 7 GIO Function 2163 37 3 RTP Control Registers 2163 37 3 1 RTP Global Control Register RTPGLBCTRL 2164 37 3 2 RTP Trace Enable Register RTPTRENA 2167 37...

Page 32: ...pyright 2018 Texas Instruments Incorporated Contents 38 4 2 EFC Pins Register EFCPINS 2193 38 4 3 EFC Error Status Register EFCERRSTAT 2194 38 4 4 EFC Self Test Cycles Register EFCSTCY 2194 38 4 5 EFC...

Page 33: ...LR offset 44h 165 2 23 GCLK1 HCLK VCLK and VCLK2 Source Register GHVSRC offset 48h 167 2 24 Peripheral Asynchronous Clock Source Register VCLKASRC offset 4Ch 168 2 25 RTI Clock Source Register RCLKSRC...

Page 34: ...ster Lower Word DIEIDL_REG2 offset F8h 215 2 71 Die Identification Register Upper Word DIEIDH_REG3 offset FCh 216 2 72 Peripheral Memory Protection Set Register 0 PMPROTSET0 offset 00h 223 2 73 Periph...

Page 35: ...CSnMSTID offset 5C0h 5DCh 251 3 1 System Level Block Diagram 254 3 2 SCM Block Diagram 255 3 3 Timeout Threshold Compare 256 3 4 SCM Control Block 256 3 5 SCM REVID Register SCMREVID offset 00h 260 3...

Page 36: ...et 38h 330 6 13 KICK_REG1 Kicker Register 1 Offset 3Ch 330 6 14 ERR_RAW_STATUS_REG Error Raw Status Set Register Offset E0h 331 6 15 ERR_ENABLED_STATUS_REG Error Enabled Status Clear Register Offset E...

Page 37: ...ector Disable Register 2 FEDACSDIS2 offset C0h 378 7 39 Lower Word of Reset Configuration Read Register RCR_VALUE0 offset D0h 379 7 40 Upper Word of Reset Configuration Read Register RCR_VALUE1 offset...

Page 38: ...Test Hardware Execution Flow Chart 440 10 8 STC Global Control Register 0 STCGCR0 offset 00h 447 10 9 STC Global Control Register 1 STCGCR1 offset 04h 448 10 10 Self Test Run Timeout Counter Preload R...

Page 39: ...Index Registers CAM_INDEXn offset 200h 21Ch 496 13 1 Block Diagram 499 13 2 CPU Input Inversion Scheme 504 13 3 CCM R5F Status Register 1 CCMSR1 Offset 00h 508 13 4 CCM R5F Key Register 1 CCMKEYR1 Of...

Page 40: ...offset 08h 567 16 14 ESM Interrupt Enable Clear Status Register 1 ESMIECR1 offset 0Ch 567 16 15 ESM Interrupt Level Set Status Register 1 ESMILSR1 offset 10h 568 16 16 ESM Interrupt Level Clear Statu...

Page 41: ...ounter 1 Register RTIUC1 offset 34h 603 17 23 RTI Compare Up Counter 1 Register RTICPUC1 offset 38h 604 17 24 RTI Capture Free Running Counter 1 Register RTICAFRC1 offset 40h 605 17 25 RTI Capture Up...

Page 42: ...ut Preload Register B CRC_BCTOPLD1 offset 50h 653 18 22 Channel 1 PSA Signature Low Register PSA_SIGREGL1 offset 60h 654 18 23 Channel 1 PSA Signature High Register PSA_SIGREGH1 offset 64h 654 18 24 C...

Page 43: ...Q3 offset 2Ch 687 19 27 Interrupt Enable Set Register 0 REQENASET0 offset 30h 688 19 28 Interrupt Enable Set Register 1 REQENASET1 offset 34h 688 19 29 Interrupt Enable Set Register 2 REQENASET2 offse...

Page 44: ...0 31 DMA Request Assignment Register 0 DREQASI0 offset 54h 731 20 32 DMA Request Assignment Register 1 DREQASI1 offset 58h 732 20 33 DMA Request Assignment Register 2 DREQASI2 offset 5Ch 733 20 34 DMA...

Page 45: ...ress Register DMAPAR offset 1ACh 767 20 81 DMA Memory Protection Control Register 1 DMAMPCTRL1 offset 1B0h 768 20 82 DMA Memory Protection Status Register 1 DMAMPST1 offset 1B4h 770 20 83 DMA Memory P...

Page 46: ...ory Interface 811 21 9 Common Asynchronous Interface 811 21 10 Timing Waveform of an Asynchronous Read Cycle in Normal Mode 815 21 11 Timing Waveform of an Asynchronous Write Cycle in Normal Mode 817...

Page 47: ...1MODECR offset 14h 890 22 28 12 bit ADC Group2 Operating Mode Control Register ADG2MODECR offset 18h 893 22 29 10 bit ADC Group2 Operating Mode Control Register ADG2MODECR offset 18h 893 22 30 ADC Eve...

Page 48: ...r ADEVTOUT offset 100h 932 22 74 ADC ADEVT Pin Input Value Register ADEVTIN offset 104h 932 22 75 ADC ADEVT Pin Set Register ADEVTSET offset 108h 933 22 76 ADC ADEVT Pin Clear Register ADEVTCLR offset...

Page 49: ...Example 972 23 11 HR I O Architecture 973 23 12 Example of HR Structure Sharing for N2HET Pins 0 1 974 23 13 XOR shared HR I O 975 23 14 Symmetrical PWM with XOR sharing Output 976 23 15 AND shared H...

Page 50: ...Level 2 Register HETOFF2 1022 23 61 Interrupt Enable Set Register HETINTENAS 1023 23 62 Interrupt Enable Clear HETINTENAC 1023 23 63 Exception Control Register HETEXC1 1024 23 64 Exception Control Re...

Page 51: ...08 HWAG Angle Increment Register HWAANGI 1059 23 109 ACMP Program Field P31 P0 1065 23 110 ACMP Control Field C31 C0 1065 23 111 ACMP Data Field D31 D0 1065 23 112 ACNT Program Field P31 P0 1067 23 11...

Page 52: ...8 MOV32 Move Operation for REGTOREM Case 10 1104 23 159 MOV32 Move Operation for REMTOREG Case 11 1104 23 160 MOV64 Program Field P31 P0 1107 23 161 MOV64 Control Field C31 C0 1107 23 162 MOV64 Data F...

Page 53: ...1153 24 21 Request Lost and Bus Error Control Register HTU RLBECTRL offset 20h 1155 24 22 Buffer Full Interrupt Enable Set Register HTU BFINTS offset 24h 1156 24 23 Buffer Full Interrupt Enable Clear...

Page 54: ...205 25 18 GIO Data Input Registers GIODIN A B offset 38h 58h 1205 25 19 GIO Data Output Registers GIODOUT A B offset 3Ch 5Ch 1206 25 20 GIO Data Set Registers GIODSET A B offset 40h 60h 1206 25 21 GIO...

Page 55: ...to System Memory Occurred 4 TSMO4 offset_TU 4Ch 1288 26 48 Transfer to Communication Controller Occurred 1 TCCO1 offset_TU 50h 1290 26 49 Transfer to Communication Controller Occurred 2 TCCO2 offset_T...

Page 56: ...2 TSMIES2 offset_TU 108h 1316 26 93 Transfer to System Memory Interrupt Enable Reset 2 TSMIER2 offset_TU 10Ch 1316 26 94 Transfer to System Memory Interrupt Enable Set 3 TSMIES3 offset_TU 110h 1317 26...

Page 57: ...ration Register 8 GTUC8 offset_CC BCh 1372 26 143 GTU Configuration Register 9 GTUC9 offset_CC C0h 1372 26 144 GTU Configuration Register 10 GTUC10 offset_CC C4h 1373 26 145 GTU Configuration Register...

Page 58: ...8 26 188 Read Header Section Register 2 RDHS2 offset_CC 704h 1409 26 189 Read Header Section Register 3 RDHS3 offset_CC 708h 1410 26 190 Message Buffer Status Register MBS offset_CC 70Ch 1411 26 191 O...

Page 59: ...gister DCAN INTPND78 offset BCh 1474 27 48 Message Valid X Register DCAN MSGVAL X offset C0h 1475 27 49 Message Valid 12 Register DCAN MSGVAL12 offset C4h 1476 27 50 Message Valid 34 Register DCAN MSG...

Page 60: ...ELAY 8 VCLK Cycles 1515 28 18 Example t T2CDELAY 4 VCLK Cycles 1516 28 19 Transmit Data Finished to ENA Inactive Timeout 1516 28 20 Chip Select Active to ENA Signal Active Timeout 1517 28 21 Typical D...

Page 61: ...TGINTFLAG offset 84h 1580 28 67 Tick Counter Operation 1581 28 68 Tick Count Register TICKCNT offset 90h 1581 28 69 Last TG End Pointer LTGPEND offset 94h 1582 28 70 MibSPI TG Control Registers TGxCTR...

Page 62: ...mmunication Format 1632 29 7 Address Bit Multiprocessor Communication Format 1632 29 8 Receive Buffers 1633 29 9 Transmit Buffers 1634 29 10 General Interrupt Scheme 1635 29 11 Interrupt Generation fo...

Page 63: ...t Buffer 0 Register LINTD0 offset 74h 1713 29 58 LIN Transmit Buffer 1 Register LINTD1 offset 78h 1713 29 59 Maximum Baud Rate Selection Register MBRS offset 7Ch 1714 29 60 Input Output Error Enable R...

Page 64: ...5 I2C Status Register I2CSR offset 08h 1784 31 16 I2C Clock Divider Low Register I2CCKL offset 0Ch 1787 31 17 I2C Clock Control High Register I2CCKH offset 10h 1787 31 18 I2C Data Count Register I2CCN...

Page 65: ...SCSTAT offset 4Ch 1864 32 26 EMAC Control Module Receive Interrupts Per Millisecond Register C0RXIMAX offset 70h 1865 32 27 EMAC Control Module Transmit Interrupts Per Millisecond Register C0TXIMAX of...

Page 66: ...15Ch 1903 32 70 MAC Control Register MACCONTROL offset 160h 1904 32 71 MAC Status Register MACSTATUS offset 164h 1906 32 72 Emulation Control Register EMCONTROL offset 168h 1908 32 73 FIFO Control Reg...

Page 67: ...ional Block Diagram of Decoder Unit 1963 34 6 Quadrature Decoder State Machine 1964 34 7 Quadrature clock and Direction Decoding 1965 34 8 Position Counter Reset by Index Pulse for 1000 Line Encoder Q...

Page 68: ...35 11 Counter Compare Submodule 2010 35 12 Detailed View of the Counter Compare Submodule 2011 35 13 Counter Compare Event Waveforms in Up Count Mode 2013 35 14 Counter Compare Events in Down Count Mo...

Page 69: ...for Note FPWM2 FPWM1 2061 35 57 Control of Two Half H Bridge Stages FPWM2 N x FPWM1 2063 35 58 Half H Bridge Waveforms for Note Here FPWM2 FPWM1 2064 35 59 Control of Dual 3 Phase Inverter Stages as...

Page 70: ...Block Diagram 2109 36 2 Trace Mode Packet Format 2111 36 3 Direct Data Mode Packet Format 2111 36 4 Packet Sync Signal Example 2113 36 5 Example Single Packet Transmission 2113 36 6 Interrupt Structur...

Page 71: ...h 2172 37 14 RTP RAM 3 Trace Region Registers RTPRAM3REGn offset 1Ch and 20h 2173 37 15 RTP Peripheral Trace Region Registers RTPPERREGn offset 24h and 28h 2175 37 16 RTP Direct Data Mode Write Regist...

Page 72: ...iptions 156 2 27 SYS Pin Control Register 9 SYSPC9 Field Descriptions 157 2 28 Clock Source Disable Register CSDIS Field Descriptions 158 2 29 Clock Sources Table 158 2 30 Clock Source Disable Set Reg...

Page 73: ...71 Secondary System Control Registers 205 2 72 PLL Control Register 3 PLLCTL3 Field Descriptions 206 2 73 CPU Logic BIST Clock Prescaler STCLKDIV Field Descriptions 207 2 74 ECP Control Register 1 EC...

Page 74: ...STID_L H Field Descriptions 243 2 118 Privileged Peripheral Frame 0 MasterID Protection Register_L PPS0MSTID_L Field Descriptions 244 2 119 Privileged Peripheral Frame 0 MasterID Protection Register_H...

Page 75: ...LOBALCTRL1 Field Descriptions 296 5 13 Global Status Register GLOBALSTAT Field Descriptions 297 5 14 PSCON Diagnostic Compare Key Register PRCKEYREG Field Descriptions 297 5 15 LogicPD PSCON Diagnosti...

Page 76: ...iptions 365 7 25 Flash Bank Access Control Register FBAC Field Descriptions 365 7 26 Flash Bank Power Mode Register FBPWRMODE Field Descriptions 366 7 27 Flash Bank Pump Ready Register FBPRDY Register...

Page 77: ...414 9 4 PBIST Activate ROM Clock Enable Register PACT Field Descriptions 415 9 5 PBIST ID Register Field Descriptions 416 9 6 Override Register OVER Field Descriptions 417 9 7 Fail Status Fail Regist...

Page 78: ...er Register MPUREGNUM Field Descriptions 482 12 1 EPC Control Registers 488 12 2 EPC REVID Register EPCREVID Field Descriptions 489 12 3 EPC Control Register EPCCNTRL Field Descriptions 490 12 4 Uncor...

Page 79: ...SM Disable ERROR Pin Action Response Register 1 ESMDEPAPR1 Field Descriptions 566 16 5 ESM Interrupt Enable Set Status Register 1 ESMIESR1 Field Descriptions 567 16 6 ESM Interrupt Enable Clear Status...

Page 80: ...RTI Compare 1 Register RTICOMP1 Field Descriptions 607 17 19 RTI Update Compare 1 Register RTIUDCP1 Field Descriptions 607 17 20 RTI Compare 2 Register RTICOMP2 Field Descriptions 608 17 21 RTI Update...

Page 81: ...criptions 656 18 26 CRC Pattern Counter Preload Register 2 CRC_PCOUNT_REG2 Field Descriptions 656 18 27 CRC Sector Counter Preload Register 2 CRC_SCOUNT_REG2 Field Descriptions 657 18 28 CRC Current S...

Page 82: ...27 20 15 SW Channel Enable Set and Status Register SWCHENAS Field Descriptions 728 20 16 SW Channel Enable Reset and Status Register SWCHENAR Field Descriptions 728 20 17 Channel Priority Set Register...

Page 83: ...FAACDADDR Field Descriptions 764 20 65 Port B Active Channel Transfer Count Register FAACTC Field Descriptions 764 20 66 FIFO B Active Channel Source Address Register FBACSADDR Field Descriptions 765...

Page 84: ...unt Register CTCOUNT Field Descriptions 792 21 1 EMIF Pins Used to Access Both SDRAM and Asynchronous Memories 796 21 2 EMIF Pins Specific to SDRAM 797 21 3 EMIF Pins Specific to Asynchronous Memory 7...

Page 85: ...Mode Control Register ADG1MODECR Field Descriptions 891 22 13 ADC Group 2 Operating Mode Control Register ADG2MODECR Field Descriptions 894 22 14 ADC Event Group Trigger Source Select Register ADEVSRC...

Page 86: ...22 59 ADC Group2 Sample Cap Discharge Control Register ADG2SAMPDISEN Field Descriptions 937 22 60 ADC Magnitude Compare Interrupt Control Registers ADMAGINTxCR Field Descriptions 939 22 61 ADC Magnit...

Page 87: ...Descriptions 1024 23 25 Exception Control Register 2 HETEXC2 Field Descriptions 1025 23 26 Interrupt Priority Register HETPRY Field Descriptions 1026 23 27 Interrupt Flag Register HETFLG Field Descri...

Page 88: ...7 HWAG Step Width Register HWASTWD Field Descriptions 1056 23 68 HWAG Teeth Number Register HWATHNB Field Descriptions 1057 23 69 HWAG Current Teeth Number Register HWATHVL Field Descriptions 1057 23...

Page 89: ...Register HTU BIM Field Descriptions 1160 24 27 Buffer Initialization 1160 24 28 Request Lost Flag Register HTU RLOSTFL Field Descriptions 1162 24 29 Buffer Full Interrupt Flag Register HTU BFINTFL Fi...

Page 90: ...eld Descriptions 1208 25 21 GIO Pull Select Registers GIOPSL A B Field Descriptions 1208 25 22 Output Buffer and Pull Control Behavior for GIO Pins 1209 26 1 FlexRay Address Range Table 1215 26 2 Flex...

Page 91: ...3 TTCCR3 Field Descriptions 1305 26 52 Trigger Transfer to Communication Controller Set 4 TTCCS4 Field Descriptions 1306 26 53 Trigger Transfer to Communication Controller Reset 4 TTCCR4 Field Descrip...

Page 92: ...ons 1343 26 98 Error Interrupt Line Select Register EILS Field Descriptions 1346 26 99 Status Interrupt Line Select Register SILS Field Descriptions 1348 26 100 Error Interrupt Set Reset Register EIES...

Page 93: ...ion 1396 26 147 New Data Registers NDATn Field Descriptions 1398 26 148 Message Buffer Status Changed Registers MBSCn Field Descriptions 1399 26 149 Core Release Register CREL Field Descriptions 1400...

Page 94: ...Descriptions 1489 27 31 IF3 Arbitration Register DCAN IF3ARB Field Descriptions 1490 27 32 IF3 Message Control Register DCAN IF3MCTL Field Descriptions 1491 27 33 IF3 Update Control Register Field De...

Page 95: ...MibSPI DMA Large Count Register DMACNTLEN Field Descriptions 1589 28 47 MibSPI Parity ECC Control Register PAR_ECC_CTRL Field Descriptions 1590 28 48 Parity ECC Status Register PAR_ECC_STAT Field Des...

Page 96: ...ITD Field Descriptions 1699 29 29 SCI Pin I O Control Register 0 SCIPIO0 Field Descriptions 1699 29 30 SCI Pin I O Control Register 1 SCIPIO1 Field Descriptions 1700 29 31 LINTX Pin Control 1700 29 32...

Page 97: ...1758 30 29 SCI Pin I O Control Register 6 SCIPIO6 Field Descriptions 1759 30 30 SCI Pin I O Control Register 7 SCIPIO7 Field Descriptions 1760 30 31 SCI Pin I O Control Register 8 SCIPIO8 Field Descri...

Page 98: ...TCONTROL 1856 32 14 EMAC Control Module Receive Threshold Interrupt Enable Register C0RXTHRESHEN 1857 32 15 EMAC Control Module Receive Interrupt Enable Register C0RXEN 1858 32 16 EMAC Control Module...

Page 99: ...Field Descriptions 1896 32 58 MAC Interrupt Mask Set Register MACINTMASKSET Field Descriptions 1897 32 59 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Field Descriptions 1897 32 60 Receive Multic...

Page 100: ...ter QPOSINIT Field Descriptions 1979 34 6 eQEP Maximum Position Count Register QPOSMAX Field Descriptions 1979 34 7 eQEP Position Compare Register QPOSCMP Field Descriptions 1980 34 8 eQEP Index Posit...

Page 101: ...iptions 2076 35 30 Counter Compare B Register CMPB Field Descriptions 2077 35 31 Action Qualifier Output A Control Register AQCTLA Field Descriptions 2078 35 32 Action Qualifier Software Force Registe...

Page 102: ...de Destination Register DMMDDMDEST Field Descriptions 2135 36 15 DMM Direct Data Mode Blocksize Register DMMDDMBL Field Descriptions 2135 36 16 DMM Direct Data Mode Pointer Register DMMDDMPT Field Des...

Page 103: ...TP Pin Control 2 Register RTPPC2 Field Descriptions 2179 37 21 RTP Pin Control 3 Register RTPPC3 Field Descriptions 2180 37 22 RTP Pin Control 4 Register RTPPC4 Field Descriptions 2181 37 23 RTP Pin C...

Page 104: ...xplains the notation used for the properties Reserved bits in a register figure can have one of multiple meanings Not implemented on the device Reserved for future device expansion Reserved for TI tes...

Page 105: ...Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers TI Embedded Proc...

Page 106: ...umentation Feedback Copyright 2018 Texas Instruments Incorporated Introduction Chapter 1 SPNU563A March 2018 Introduction Topic Page 1 1 Designed for Safety Applications 107 1 2 Family Description 108...

Page 107: ...l of diagnostic coverage for the lockstep CPUs and SRAMs in the system while executing faster and consuming less memory than equivalent software based self test solutions Hardware BIST diagnostic also...

Page 108: ...measurements of the three temperature sensors are routed to the MibADC for conversion into digital values CPU can read out the digital values and compare with the calibrated temperature value stored...

Page 109: ...veral interfaces are implemented to enhance the debugging capabilities of application code In addition to the built in ARM Cortex R5F CoreSight debug features Embedded Cross Trigger ECT supports the i...

Page 110: ...PWMxA ePWMxB N2HET1 FlexRay GIO N2HET2 FRAY_RX1 FRAY_TX1 FRAY_TXEN1 FRAY_RX2 FRAY_TX2 FRAY_TXEN2 GIOB 7 0 GIOA 7 0 N2HET1 31 0 N2HET1_PIN_nDIS N2HET2_PIN_nDIS MibADC1 MibADC2 VSSAD VCCAD ADREFHI ADREF...

Page 111: ...C2EDELAY 7 0 Byte 1 0xFFF7F44A Byte 0 0xFFF7F44B 32 bit accesses to this register should use the lowest address that is 0xFFF7F448 Writing 0x11223344 to address 0xFFF7F448 shows the following when vie...

Page 112: ...e architecture The second section describes the clocking structure of the microcontrollers The third section gives an overview of the device memory organization The fourth section details exceptions o...

Page 113: ...h glues the masters and slaves together The CPU safety island contains high degree of safety diagnostics on the bus system and the memories Memories and buses are protected by means of ECC on the data...

Page 114: ...M w ECC NMPU NMPU STC1 EPC SCM SYS DCC2 STC2 DMM DAP CCM R5F MibSPI2 MibSPI3 MibSPI4 LIN1 SCI1 LIN2 SCI2 SCI3 SCI4 I2C1 I2C2 FlexRay GIO N2HET1 N2HET2 MibADC1 MibADC2 ESM MibSPI5 CRC1 Dma_portA uSCU S...

Page 115: ...device memory map The DAP is a bus master in this device DCANx Controller Area Network controller The DCAN supports the CAN 2 0B protocol standard and uses a serial multi master communication protocol...

Page 116: ...le this provides an interface between the EMAC and MDIO modules and the bus masters It also includes 8KB of RAM to hold EMAC packet buffer descriptors 2 EMAC The EMAC module interfaces to the other de...

Page 117: ...purpose I O NMPUx Enhanced Memory Protection Unit There are three standalone NMPUs on this device protecting memory transactions initiated by DMA EMAC and other masters onto the resources on the devi...

Page 118: ...ic Logic Bist Controller as the test engine The other STC is used to test either or both the N2HETs in the device SYS System Module This module contains the housekeeping logic to control and log overa...

Page 119: ...to the system that are captured in the SCM SCR Control Module Table 4 4 lists the SCM register bit mapping 2 1 6 Master ID to PCRx The master ID associated with each master port on the Peripheral Inte...

Page 120: ...on the ARM Cortex R5F processor core starts execution from the reset vector address of 0x00000000 whenever the core gets reset The CPU data RAM is addressed starting at 0x08000000 by default The devic...

Page 121: ...2 0xFC000000 0xFCFFFFFF EMIF 128MB 0x80000000 0x9FFFFFFF CS0 RESERVED reserved Async RAM SDRAM 0x64000000 0x68000000 0x6C000000 Flash Flash ECC OTP and EEPROM accesses 0xF047FFFF Peripherals Frame 3...

Page 122: ...tor Coherency Port 0x0800_0000 0x087F_FFFF 8MB 512kB Abort Level 1 Cache Memories Cortex R5F Data Cache Memory 0x3000_0000 0x30FF_FFFF 16MB 32kB Abort Cortex R5F Instruction Cache Memory 0x3100_0000 0...

Page 123: ..._8C00 0xFCF7_8CFF 256B 256B Abort ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort ePWM5 PS 27 0xFCF7_9000 0xFC...

Page 124: ...F 128kB 4kB Abort for accesses above 4KB DCAN4 RAM PCS 12 0xFF18_0000 0xFF19_FFFF 128kB 8kB Abort generated for accesses beyond offset 0x2000 DCAN3 RAM PCS 13 0xFF1A_0000 0xFF1B_FFFF 128kB 8kB Abort g...

Page 125: ...around for accesses to unimplemented address offsets lower than 0x3FFF Abort generated for accesses beyond 0x3FFF NHET1 RAM PCS 35 0xFF46_0000 0xFF47_FFFF 128kB 16kB Wrap around for accesses to unimpl...

Page 126: ...es have no effect FTU PS 23 0xFFF7_A000 0xFFF7_A1FF 512B 512B Reads return zeros writes have no effect HTU1 PS 22 0xFFF7_A400 0xFFF7_A4FF 256B 256B Abort HTU2 PS 22 0xFFF7_A500 0xFFF7_A5FF 256B 256B A...

Page 127: ...PI2 PS 2 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros writes have no effect MibSPI3 PS 1 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros writes have no effect MibSPI4 PS 1 0xFFF7_FA00 0xF...

Page 128: ...B 512B Reads return zeros writes have no effect STC1 Cortex R5F PPS 1 0xFFFF_E600 0xFFFF_E6FF 256B 256B Reads return zeros writes have no effect DCC1 PPS 3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads retu...

Page 129: ...use as emulated EEPROM Refer to the device data manual for electrical and timing specifications related to the flash module 2 2 3 1 Flash Bank Sectoring Configuration The bank is divided into multipl...

Page 130: ..._0000 0x000F_FFFF 12 256K Bytes 0x0010_0000 0x0013_FFFF 13 256K Bytes 0x0014_0000 0x0017_FFFF 14 256K Bytes 0x0018_0000 0x001B_FFFF 15 256K Bytes 0x001C_0000 0x001F_FFFF Bank 1 2 0 Mbytes 0 128K Bytes...

Page 131: ...is first captured by the Error Profiling Controller EPC module and in turn generates error signals that are input to the central Error Signaling Module ESM 2 2 3 3 Error Profiling Module EPC The main...

Page 132: ...ectable ECC for DMA I F CPU SCR Uncorrectable ECC for PS_SCR_M I F Err Gen Uncorrectable Error Capture Block UERR Addr Reg UERR Addr Reg Err Stat Err Stat EPC Module Correctable Error Event Source Uno...

Page 133: ...R_M interface Bit associates with the FIFO full status for the interface that is used to capture the PS_SCR_M correctable error event Correctable error event detected by the CPU Interconnect Subsystem...

Page 134: ...o takes into account the read protection scheme implemented for each SRAM module ECC or parity TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto initialization Th...

Page 135: ...6 Single port 11 Single port 16 Single port 21 Single port 26 Single port R5_ICACHE 31 40 1 Single port 6 Single port 11 Single port 16 Single port R5_DCACHE 32 41 1 Single port 6 Single port 11 Sing...

Page 136: ...ROM 1 2 3 4 0x0000000F 0x00000000 3 0x00000004 march13n Two port 0x00000000 0x96699669 0x0F0F0F0F 0xAA55AA55 0xC3C3C3C3 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 0x0FFFBFF0 0x000...

Page 137: ...ased on their error detection scheme odd even parity or ECC For example the contents of the CPU level 2 SRAM after power on reset is unknown A hardware auto initialization can be started so that there...

Page 138: ...ecting Module Memory Protection Scheme Address Range SYS MSINENA Register Bit L2RAMW MEMINT_ENA Register Bit 3 Base Address Ending Address L2 SRAM ECC 0x08000000 0x0800FFFF 0 0 L2 SRAM ECC 0x08010000...

Page 139: ...the PORST bit in the SYSESR register SYSESR 15 Note The voltage monitor is not an alternative for an external voltage supervisor Driving nRST pin low externally Warm reset This reset input is typical...

Page 140: ...s the data until the memory system has sufficient bandwidth to perform the write access This gives read accesses higher priority The write data can be held in the buffer for a long period during which...

Page 141: ...e of operation If the CPU writes to these registers in user mode the writes are ignored The PCR module PMPROTSETx registers contain one bit per peripheral memory frame These bits define the access per...

Page 142: ...rnal reference oscillator This is typically a 10 MHz signal CLK10M that is used by the clock monitor module as a reference clock to monitor the main oscillator frequency 6 PLL2 This is the output of t...

Page 143: ...DIV register at address 0xFFFFE108 HCLK CDDIS 1 OSCIN GHVSRC 3 0 Divided from GCLK1 via HCLKCNTL register Allowable clock ratio from 1 1 to 4 1 Is disabled via the CDDISx registers bit 1 VCLK CDDIS 2...

Page 144: ...are control registers that allow an application to choose the clock sources for each clock domain Selecting clock source for GCLK1 HCLK and VCLKx domains The CPU clock GCLK1 the system module clock H...

Page 145: ...cal characteristics They are not the only low power modes configurable by the application as just described Table 2 11 Typical Low Power Modes Mode Name Active Clock Source s Active Clock Domain s Wak...

Page 146: ...Ux FlexRay Transfer Unit FTU and Parameter Overlay Module POM can have ongoing transactions when the application wants to enter a low power mode to turn off the clocks to those modules This is not rec...

Page 147: ...served 0010 Reserved 00011 EXTCLKIN1 0011 Reserved 00100 Low frequency LPO Low Power Oscillator clock CLK80K 0100 Reserved 00101 High frequency LPO Low Power Oscillator clock CLK10M 0101 HF LPO Clock...

Page 148: ...n is done by the EXTCTLOUT control bits of the TPIU EXTCTL_Out_Port register The address of this register is TPIU base address 0x404 Before you begin accessing TPIU registers the TPIU should be unlock...

Page 149: ...ged in the system module global status register the application can choose the device s response to the slip indication Refer to Chapter 14 for more details on PLL slip and the system response choices...

Page 150: ...ck Signal Name Ah 0h PLL1 free running clock output 1h PLL2 free running clock output 2h LF LPO 3h HF LPO 4h Flash pump oscillator 5h EXTCLKIN1 6h EXTCLKIN2 7 Reserved 8h Fh VCLK All other values any...

Page 151: ...CSDISCLR Clock Source Disable Clear Register Section 2 5 1 12 3Ch CDDIS Clock Domain Disable Register Section 2 5 1 13 40h CDDISSET Clock Domain Disable Set Register Section 2 5 1 14 44h CDDISCLR Clo...

Page 152: ...40 CCh CPURSTCR CPU Reset Control Register Section 2 5 1 41 D0h CLKCNTL Clock Control Register Section 2 5 1 42 D4h ECPCNTL ECP Control Register Section 2 5 1 43 DCh DEVCR1 DEV Parity Control Register...

Page 153: ...ut Note Proper ECLK duty cycle is not guaranteed until 1 ECLK cycle has elapsed after switching into functional mode 2 5 1 2 SYS Pin Control Register 2 SYSPC2 The SYSPC2 register shown in Figure 2 9 a...

Page 154: ...PC4 The SYSPC4 register shown in Figure 2 11 and described in Table 2 22 controls the logic level output function of the ECLK pin when it is configured as an output in GIO mode Figure 2 11 SYS Pin Con...

Page 155: ...is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register 2 5 1 6 SYS Pin Contro...

Page 156: ...s driven low ECPCLKDOUT 1 The ECLK output buffer is tristated Note The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the SYSPC1 register 2 5 1 8 SYS Pin Control Register 8 SYS...

Page 157: ...t Table 2 27 SYS Pin Control Register 9 SYSPC9 Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reads return 0 Writes have no effect 0 ECPCLKPS ECLK pull up pull down select This bit is...

Page 158: ...sable Register CSDIS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 3 CLKSR 7 3 OFF Clock source 7 3 off 0 Clock source 7 3 is enabled 1 Clock so...

Page 159: ...no effect 7 3 SETCLKSR 7 3 OFF Set clock source 7 3 to the disabled state 0 Read Clock source 7 3 is enabled Write Clock source 7 3 is unchanged 1 Read Clock source 7 3 is disabled Write Clock source...

Page 160: ...s return 0 Writes have no effect 7 3 CLRCLKSR 7 3 OFF Enables clock source 7 3 0 Read Clock source 7 3 is enabled Write Clock source 7 3 is unchanged 1 Read Clock source 7 3 is enabled Write Clock sou...

Page 161: ...CLKA4OFF Reserved Reserved VCLK3OFF R 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 Reserved RTICLK1OFF VCLKA2OFF VCLKA1OFF VCLK2OFF VCLKPOFF HCLKOFF GCLK1OFF R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0...

Page 162: ...porated Architecture Table 2 32 Clock Domain Disable Register CDDIS Field Descriptions continued Bit Field Value Description 1 HCLKOFF HCLK and VCLK_sys domains off 0 The HCLK and VCLK_sys domains are...

Page 163: ...1 SETVCLKA4OFF Set VCLKA4 domain 0 Read The VCLKA4 domain is enabled Write The VCLKA4 domain is unchanged 1 Read The VCLKA4 domain is disabled Write The VCLKA4 domain is set to the enabled state 10 9...

Page 164: ...K_periph domain is unchanged 1 Read The VCLK_periph domain is disabled Write The VCLK_periph domain is set to the enabled state 1 SETHCLKOFF Set HCLK and VCLK_sys domains 0 Read The HCLK and VCLK_sys...

Page 165: ...FF Clear VCLKA4 domain 0 Read The VCLKA4 domain is enabled Write The VCLKA4 domain is unchanged 1 Read The VCLKA4 domain is disabled Write The VCLKA4 domain is cleared to the enabled state 10 9 Reserv...

Page 166: ...ph domain is unchanged 1 Read The VCLK_periph domain is disabled Write The VCLK_periph domain is cleared to the enabled state 1 CLRHCLKOFF Clear HCLK and VCLK_sys domains 0 Read The HCLK and VCLK_sys...

Page 167: ...for GCLK1 HCLK VCLK on wakeup 7h Clock source7 is the source for GCLK1 HCLK VCLK on wakeup 8h Fh Reserved 23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 HVLPM HCLK VCLK VCLK2 source on w...

Page 168: ...Writes have no effect 11 8 VCLKA2S Peripheral asynchronous clock2 source 0 Clock source0 is the source for peripheral asynchronous clock2 1h Clock source1 is the source for peripheral asynchronous clo...

Page 169: ...7 4 3 0 Reserved RTI1DIV Reserved RTI1SRC R 0 R WP 1h R 0 R WP 9h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 37 RTI Clock Source Register RCLKSRC F...

Page 170: ...ck Source Valid Register CSVSTAT Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 3 CLKSR 7 3 V Clock source 7 0 valid 0 Clock source 7 0 is not va...

Page 171: ...and depends on what is written in privileged mode The functionality of these bits are unavailable in this device 15 10 Reserved 0 Reads return 0 Writes have no effect 9 8 ROM_DIV Prescaler divider bi...

Page 172: ...4 3 0 Reserved MINITGENA R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 40 Memory Hardware Initialization Global Control Register MINITGCR...

Page 173: ...test mode all the corresponding bits of the memories to be tested should be set before enabling the global memory self test controller key MSTGENA in the MSTGCR register offset 58h The reason for thi...

Page 174: ...ns Bit Field Value Description 31 9 Reserved 0 Reads return 0 Writes have no effect 8 MINIDONE Memory hardware initialization complete status Note Disabling the MINITGENA key By writing from a Ah to a...

Page 175: ...hardware initialization status bit 0 Read Memory module 31 0 hardware initialization is not completed Write A write of 0 has no effect 1 Read Memory module 31 0 hardware initialization is completed Wr...

Page 176: ...a PLL Slip and the PLL will be bypassed after the reset occurs 28 24 PLLDIV PLL Output Clock Divider R PLLDIV 1 f PLL CLK f post_ODCLK R 0 f PLL CLK f post ODCLK 1 1h f PLL CLK f post ODCLK 2 1Fh f PL...

Page 177: ...INGRATE NS SPREADINGRATE 1 f mod f s f INT CLK 2 NS 0 f mod f s f INT CLK 2 1 1h f mod f s f INT CLK 2 2 1FFh f mod f s f INT CLK 2 512 21 Reserved 0 Value has no effect on PLL operation 20 12 MULMOD...

Page 178: ...e 2 34 SYS Pin Control Register 10 SYSPC10 offset 78h 31 16 Reserved R 0 15 1 0 Reserved ECPCLK_SLEW R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 2 46 SYS Pin Control Register...

Page 179: ...nate of the device 11 0 X WAFER COORDINATE These read only bits contain the X wafer coordinate of the device NOTE Die Identification Information The die identification information will vary from unit...

Page 180: ...5 4 0 Reserved HFTRIM Reserved LFTRIM R 0 R WP 10h R 0 R WP 10h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 49 LPO Clock Monitor Control Register LP...

Page 181: ...Caution This value should only be changed when the HF oscillator is not the source for a clock domain otherwise a system failure could result The following values are the ratio f fo in the F021 proce...

Page 182: ...LF oscillator s frequency Caution This value should only be changed when the LF oscillator is not the source for a clock domain otherwise a system failure could result The following values are the ra...

Page 183: ...o 0 25 RANGEDETCTRL Range detection control This bit s functionality is dependant on the state of the RANGEDETENSSEL bit Bit 24 of the CLKTEST register 0 The clock monitor range detection circuitry RA...

Page 184: ...scillator valid status Dh Reserved Eh VCLKA4 Fh Oscillator valid status 7 5 Reserved 0 Reads return 0 Writes have no effect 4 0 SEL_ECP_PIN ECLK pin clock source select Note Only valid clock sources c...

Page 185: ...1 configured in fast mode DFTWRITE 0 1 and DFTREAD 0 1 configured in slow mode DFTWRITE 1 0 and DFTREAD 1 0 configured in slow mode DFTWRITE 0 1 and DFTREAD 0 1 configured in screen mode DFTWRITE 1 1...

Page 186: ...27 12 R WP 0 15 4 3 0 IMPDF 11 0 TEST_MODE_KEY R WP 0 R WP 5h LEGEND R W Read Write WP Write in privileged mode only n value after reset Table 2 52 DFT Control Register 2 DFTCTRLREG2 Field Descriptio...

Page 187: ...nt reaches 0 if the synchronized FBSLIP signal is still high an FBSLIP condition is indicated to the system module and is captured in the global status register When the FBSLIP signal from the PLL mac...

Page 188: ...6 Reserved 0 Reads return 0 Writes have no effect 15 8 SSKEY1 0 FFh System software interrupt request key A 075h written to these bits initiates IRQ FIQ interrupts Data in this field is always read as...

Page 189: ...ns Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 SSKEY2 0 FFh System software interrupt2 request key A 84h written to these bits initiates IRQ FIQ interrupts D...

Page 190: ...ons Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 SSKEY3 0 FFh System software interrupt request key A 93h written to these bits initiates IRQ FIQ interrupts D...

Page 191: ...ns Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 SSKEY4 0 FFh System software interrupt2 request key A A2h written to these bits initiates IRQ FIQ interrupts D...

Page 192: ...have no effect 14 Reserved 0 1 Reads return 0 or 1 depends on what is written in privileged mode The functionality of this bit is unavailable in this device 13 Reserved 0 Reads return 0 Writes have n...

Page 193: ...ite R Read only WP Write in privileged mode only n value after reset Table 2 59 Bus Matrix Module Control Register 1 BMMCR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0...

Page 194: ...itten as a single bit is actually a multi bit key with error correction capability As such single bit flips within the key can be corrected allowing protection of the system as a whole An error detect...

Page 195: ...NA Reserved R 0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 61 Clock Control Register CLKCNTL Field Descriptions Bit Field Value Descripti...

Page 196: ...ription 31 25 Reserved 0 Reads return 0 Writes have no effect 24 ECPSSEL This bit allows the selection between VCLK and OSCIN as the clock source for ECLK Note Other ECLK clock sources are available f...

Page 197: ...evice parity is odd 2 5 1 45 System Exception Control Register SYSECR The SYSECR register shown in Figure 2 52 and described in Table 2 64 is used to generate a software reset NOTE The register bits i...

Page 198: ...a power on reset This bit should be cleared after being read so that subsequent resets can be properly identified as not being power on resets 14 OSCRST Reset caused by an oscillator failure or PLL c...

Page 199: ...PURSTCR register 0 No CPU reset has occurred 1 A CPU reset occurred 4 SWRST Software reset flag This bit is set when a software system reset has occurred Write 1 will clear this bit Write 0 has no eff...

Page 200: ...n if any completed successfully This is also the value that the error status register is set to after reset 1h Read Controller times out because there is no last row sent from the FuseROM 2h Read The...

Page 201: ...er GLBSTAT Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reads return 0 Writes have no effect 9 FBSLIP PLL over cycle slip detection cleared by nPORRST maintains its previous value f...

Page 202: ...by device configuration 16 13 TECH These bits define the process technology by which the device was manufactured 0 Device manufactured in the C05 process technology 1h Device manufactured in the F05...

Page 203: ...key value of the source for the system software interrupt which is indicated by the vector in the SSIVEC 7 0 field 7 0 SSIVECT These bits contain the source for the system software interrupt Note A r...

Page 204: ...R WC 0 R WC 0 R WC 0 R WC 0 LEGEND R W Read Write R Read only C Clear n value after reset Table 2 70 System Software Interrupt Flag Register SSIF Field Descriptions Bit Field Value Description 31 4 R...

Page 205: ...gister 3 Section 2 5 2 1 08h STCLKDIV CPU Logic BIST Clock Divider Section 2 5 2 2 24h ECPCNTL ECP Control Register The ECPCNTL register has the mirrored location at this address Section 2 5 1 43 28h...

Page 206: ...foutput_CLK2 OD2 Note PLL output clock is gated off if ODPLL2 is changed while the PLL 2 is active 0 fpost_ODCLK2 foutput_CLK2 1 1h fpost_ODCLK2 foutput_CLK2 2 7h fpost_ODCLK2 foutput_CLK2 8 28 24 PL...

Page 207: ...PU Logic BIST Clock Prescaler STCLKDIV offset 08h 31 27 26 24 23 16 Reserved CLKDIV Reserved R 0 R WP 0 R 0 15 0 Reserved R 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value...

Page 208: ...NTL1 Field Descriptions Bit Field Value Description 31 28 ECP_KEY Enable ECP clock logic for ECLK2 Ah Clock functionality of ECP clock is enabled Others Clock functionality of ECP clock is disabled 27...

Page 209: ...served R 0 15 12 11 8 7 4 3 0 Reserved Reserved Reserved VCLK3R R 0 R WP 1h R 0 R WP 1h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 75 Clock 2 Contro...

Page 210: ...ock is disabled when VCLKA4 clock is disabled 0 The ratio is VCLKA4 divided by 1 7h The ratio is VCLKA4 divided by 8 23 21 Reserved 0 Reads return 0 Writes have no effect 20 VCLKA4_DIV_CDDIS Disable t...

Page 211: ...Reserved R 0 15 2 1 0 Reserved HCLKR R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 77 HCLK Control Register HCLKCNTL Field Descriptions Bit...

Page 212: ..._RFSLIP_FILTER_COUNT PLL RFSLIP down counter programmed value Count is on 10M clock On reset counter value is 0 Counter must be programmed to a non zero value and enabled for the filtering to be enabl...

Page 213: ...tes have no effect 11 8 IP2_ECC_KEY ECC Error Enable Key for PS_SCR_M master There is an ECC Evaluation block inside the CPU Interconnect Subsystem responsible for ECC correction and detection on the...

Page 214: ...ctions Program ProgramCRA RunAutoload and LoadFuseScanchain in EFC registers is blocked 2 5 2 10 Die Identification Register Lower Word DIEIDL_REG0 The DIEIDL_REG0 register is a duplicate of the DIEID...

Page 215: ...criptions Bit Field Description 31 24 Reserved Reserved for TI use Writes have no effect 23 0 LOT This read only register contains the device lot number NOTE Die Identification Information The die ide...

Page 216: ...71 and described in Table 2 84 Figure 2 71 Die Identification Register Upper Word DIEIDH_REG3 offset FCh 31 0 DIEIDH2 R X LEGEND R Read only X value is unchanged after reset n value after reset Table...

Page 217: ...eripheral Protection Set Register 1 Section 2 5 3 6 28h PPROTSET2 Peripheral Protection Set Register 2 Section 2 5 3 7 2Ch PPROTSET3 Peripheral Protection Set Register 3 Section 2 5 3 8 40h PPROTCLR0...

Page 218: ...3 32 360h PS12MSTID_L Peripheral Frame 12 Master ID Protection Register_L Section 2 5 3 32 364h PS12MSTID_H Peripheral Frame 12 Master ID Protection Register_H Section 2 5 3 32 368h PS13MSTID_L Perip...

Page 219: ...egister_L Section 2 5 3 35 414h PPS2MSTID_H Privileged Peripheral Frame 2 Master ID Protection Register_H Section 2 5 3 35 418h PPS3MSTID_L Privileged Peripheral Frame 3 Master ID Protection Register_...

Page 220: ...tion 2 5 3 38 498h PPSE11MSTID_L Privilege Peripheral Extended Frame 11 Master ID Protection Register_L Section 2 5 3 38 49Ch PPSE11MSTID_H Privilege Peripheral Extended Frame 11 Master ID Protection...

Page 221: ...ended Frame 25 Master ID Protection Register_L Section 2 5 3 38 50Ch PPSE25MSTID_H Privilege Peripheral Extended Frame 25 Master ID Protection Register_H Section 2 5 3 38 510h PPSE26MSTID_L Privilege...

Page 222: ...tion 2 5 3 39 590h PCS20MSTID Peripheral Memory Frame Master ID Protection Register20 Section 2 5 3 39 594h PCS21MSTID Peripheral Memory Frame Master ID Protection Register21 Section 2 5 3 39 598h PCS...

Page 223: ...framen can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is set to 1 2 5 3 2 Peripheral...

Page 224: ...en can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared to 0 2 5 3 4 Peripheral...

Page 225: ...he slave uses only one quadrant In this case the bit as specified in Table 2 90 protects the slave The above arrangement is true for all the peripheral selects PS0 to PS31 presented in Section 2 5 3 6...

Page 226: ...quadrant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET1 and PPROTCLR1 registers is set to 1 2 5 3 7 Peripheral...

Page 227: ...adrant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET3 and PPROTCLR3 registers is set to 1 2 5 3 9 Peripheral Pr...

Page 228: ...rant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET1 and PPROTCLR1 registers is cleared to 0 2 5 3 11 Peripheral...

Page 229: ...and reads are 0 Figure 2 83 Peripheral Protection Clear Register 3 PPROTCLR3 offset 4Ch 31 0 PS 31 24 QUAD 3 0 PROTCLR R WP 0 LEGEND R W Read Write WP Write in privileged mode only n value after reset...

Page 230: ...clock power down set 0 Read The peripheral memory clock 31 0 is active Write The bit is unchanged 1 Read The peripheral memory clock 31 0 is inactive Write The corresponding bit in the PCSPWRDWNSET0...

Page 231: ...s active Write The bit is unchanged 1 Read The peripheral memory clock 31 0 is inactive Write The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers is cleared to 0 2 5 3 16 Peripheral...

Page 232: ...in a frame are identical to what is described under PPROTSET0 Section 2 5 3 5 This arrangement is the same for bits of PS8 to PS31 presented in Section 2 5 3 18 Section 2 5 3 24 This register holds bi...

Page 233: ...active Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is set to 1 2 5 3 19 Peripheral...

Page 234: ...ctive Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is set to 1 2 5 3 21 Peripheral P...

Page 235: ...ive Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is cleared to 0 2 5 3 23 Peripheral...

Page 236: ...3 PSPWRDWNCLR3 Field Descriptions Bit Field Value Description 31 0 PS 31 24 QUAD 3 0 PWRDWNCLR Peripheral select quadrant clock power down clear 0 Read The clock to the peripheral select quadrant is...

Page 237: ...nactive Write Clear the bit to 0 2 5 3 27 MasterID Protection Write Enable Register MSTIDWRENA Figure 2 98 MasterID Protection Write Enable Register MSTIDWRENA offset 200h 31 16 Reserved R 0 15 4 3 0...

Page 238: ...R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 113 MasterID Enable Register MSTIDENA Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reads retur...

Page 239: ...as a bus error After the diagnostic mode is enabled in DIAG_MODE_ENA register and a diagnostic compare value is programmed into the DIAG_CMP_VALUE register the application must issue a dummy diagnost...

Page 240: ...2 101 and described in Table 2 115 Figure 2 101 Peripheral Frame 0 MasterID Protection Register_L PS0MSTID_L offset 300h 31 16 PS0_QUAD1_MSTID R WP FFFFh 15 0 PS0_QUAD0_MSTID R WP FFFFh LEGEND R W Rea...

Page 241: ...escription 15 0 PS0_QUAD0_MSTID MasterID filtering for Quadrant 0 of PS 0 0 Read The corresponding master ID is not permitted to access the peripheral mapped to this quadrant Write Disable the permiss...

Page 242: ...ral Frame 0 MasterID Protection Register_H PS0MSTID_H Field Descriptions Bit Field Value Description 31 16 PS0_QUAD3_MSTID MasterID filtering for Quadrant 3 of PS 0 0 Read The corresponding master ID...

Page 243: ...SnMSTID_L H Field Descriptions Bit Field Value Description 31 16 PSn_QUAD3_MSTID or PSn_QUAD1_MSTID n 1 to 31 L quadrant0 and quadrant1 H quadrant2 and quadrant3 MasterID filtering for Quadrant 3 of P...

Page 244: ...ister bits a If bits 15 0 are 1010_1010_1010_1010 then the peripheral that is mapped to Quadrant 0 of PPS 0 can be addressed by Masters with Master ID equals to 1 3 5 7 9 11 13 15 b if bits 15 0 are 0...

Page 245: ...n Bit Field Value Description 31 16 PPS0_QUAD3_MSTID MasterID filtering for Quadrant 3 of PPS 0 0 Read The corresponding master ID is not permitted to access the peripheral Write Disable the permissio...

Page 246: ...UAD3_MSTID or PPSn_QUAD1_MSTID n 1 to 7 L quadrant0 and quadrant1 H quadrant2 and quadrant3 MasterID filtering for Quadrant 3 of PPS n or Quadrant 1 of PPS n 0 Read The corresponding master ID is not...

Page 247: ...age of these register bits a If bits 15 0 are 1010_1010_1010_1010 then the peripheral that is mapped to Quadrant 0 of PPSE 0 can be addressed by Masters with Master ID equals to 1 3 5 7 9 11 13 15 b i...

Page 248: ...eld Descriptions Bit Field Value Description 31 16 PPSE0_QUAD3_MSTID MasterID filtering for Quadrant 3 of PPSE 0 0 Read The corresponding master ID is not permitted to access the peripheral Write Disa...

Page 249: ...31 16 PPSEn_QUAD3_MSTID or PPSEn_QUAD1_MSTID n 1 to 31 L quadrant0 and quadrant1 H quadrant2 and quadrant3 MasterID filtering for Quadrant 3 of PPSE n or Quadrant 1 of PPSE n 0 Read The corresponding...

Page 250: ...alue Description 31 16 PCS 2n 1 _MSTID MasterID filtering for PCS 2n 1 where n 0 to 31 0 Read The corresponding master ID is not permitted to access the peripheral Write Disable the permission of the...

Page 251: ...tions Bit Field Value Description 31 16 PPCS 2n 1 _MSTID MasterID filtering for PPCS 2n 1 where n 0 to 7 0 Read The corresponding master ID is not permitted to access the peripheral Write Disable the...

Page 252: ...ments Incorporated SCR Control Module SCM Chapter 3 SPNU563A March 2018 SCR Control Module SCM This chapter describes the SCR control module SCM SCR is the CPU Interconnect Subsystem Topic Page 3 1 Ov...

Page 253: ...me counter is equal or larger than the threshold the SCM will trigger an error event to ESM A corresponding status bit of the corresponding IA will also be set Compares the real time running counter o...

Page 254: ...SCM and interconnect SCR SCM compares the transaction command request to transaction command accept req2accept counters and transaction command request to transaction command response req2resp counter...

Page 255: ...re 3 3 takes the real time counters command request to command accepted and command request to command response from each IA of the interconnect hardware checker module and compare against the corresp...

Page 256: ...ruments Incorporated SCR Control Module SCM Figure 3 3 Timeout Threshold Compare 3 2 2 1 Interconnect Timeout Clearing Control Key When the threshold compare block triggers a time out error the ESM wi...

Page 257: ...re checker logic whenever you decide at appropriate time in the application control loop The self test logic will create normal and erroneous transaction from each master to each slave according to th...

Page 258: ...t control register Interconnect SDC MMR offset at 0xFA00_0000 0 is 0 2 Software needs to ensure that GCLK1 is still running 3 Software needs to ensure that all bus master connecting to interconnect sh...

Page 259: ...decimal 1024 400h for the SCMTHRESHOLD control registers However you can change this values depending on application depending on the number of IA and TA required by the interconnect When threshold c...

Page 260: ...rs Offset Acronym Register Description Section 00h SCMREVID SCM REVID Register Section 3 4 1 04h SCMCNTRL SCM Control Register Section 3 4 2 08h SCMTHRESHOLD SCM Compare Threshold Counter Register Sec...

Page 261: ...eserved Write in Privilege Ah Parity diagnostic enable All other values Reserved 23 20 Reserved 0 Reserved Reads return 0 19 16 GLOBAL_ERROR_CLR Clear global error in interconnect Writing Ah sends out...

Page 262: ...4 SCM Compare Threshold Counter Register SCMTHRESHOLD Field Descriptions Bit Field Value Description 31 16 REQ2RESPONSE_MAX 0 FFFFh Request to Response Threshold values You need to configure the maxim...

Page 263: ...pping of each R2An to a particular IP Read 0 No request to accept time out error happens on IAn 1 Request to accept time out error happens on IAn Write in Privilege 0 No effect 1 Clear this flag bit 3...

Page 264: ...the corresponding IAn Refer to Interconnect chapter of the TRM for mapping of master port to the SCMIASTAT register bit 0 No pending transaction in IAn 1 Pending transaction in IAn 3 4 7 SCM Target Ac...

Page 265: ...struments Incorporated Interconnect Chapter 4 SPNU563A March 2018 Interconnect This chapter describes the two interconnects in the microcontroller Topic Page 4 1 Overview 266 4 2 Peripheral Interconne...

Page 266: ...Figure 4 1 is a block diagram of the Interconnects implemented in this family of microcontrollers Figure 4 1 Interconnect Block Diagram 4 2 Peripheral Interconnect Subsystem There are masters and sla...

Page 267: ...unexpected transaction sent by the master ERR_TRANS_ID PS_SCR_ M POM DMA_ PORTA CPU AXI M Reserved ACP M Reserved Error related to mismatch on the transaction ID ERR_TRANS_ SIGNATURE PS_SCR_ M POM DM...

Page 268: ..._M See 1 No No Yes No No No 4 3 1 Slave Accessing 4 3 1 1 Accessing L2 Flash Slave There are two flash slave ports which allow possible parallel requests by the masters to different flash banks at the...

Page 269: ...apter for more information DMA PortA and PS_SCR_M masters do not have built in ECC generation and evaluation logic Therefore the CPU Interconnect Subsystem contain a standalone ECC generation and eval...

Page 270: ...ET bits is automatically reverted back to 0x5 as the reset value 5 After the self test is complete a reset is applied to the CPU Interconnect Subsystem for 16 HCLK cycles During this time the CPU is a...

Page 271: ...responding to the master that is detected by the interconnect checker to have a fault A timeout error when the time the request is issued by the master until the time the request is accepted by the sl...

Page 272: ...h SDC_CONTROL SDC Control Register Section 4 4 2 8h ERR_GENERIC_PARITY Error Generic Parity Register Section 4 4 3 Ch ERR_UNEXPECTED_TRANS Error Unexpected Transaction Register Section 4 4 4 10h ERR_T...

Page 273: ...indicates that one safety diagnostic checker has asserted an error input that is captured in error log registers located at address offset from 0x08 to 0x28 0 No error is detected by any checker 1 Err...

Page 274: ...t 1 Disable SCM to launch self test on the interconnect 4 4 3 Error Generic Parity Register ERR_GENERIC_PARITY Figure 4 4 Error Generic Parity Register ERR_GENERIC_PARITY offset 08h 31 16 Reserved R 0...

Page 275: ...corresponding to the master is detected by the interconnect checker to have a fault bit 0 PS_SCR_M master bit 1 POM master bit 2 DMA PortA master bit 3 Reserved bit 4 Cortex R5F CPU master bit 5 ACP M...

Page 276: ...ain and compared to the original signature When set each bit indicates the transaction processing block inside the interconnect corresponding to the master is detected by the interconnect checker to h...

Page 277: ...PS_SCR_M master bit 1 POM master bit 2 DMA PortA master bit 3 Reserved bit 4 Cortex R5F CPU master bit 5 ACP M master 4 4 9 Slave Error Unexpected Master ID Register SERR_UNEXPECTED_MID Figure 4 10 S...

Page 278: ...have a fault bit 0 L2 SRAM slave bit 1 L2 Flash PortB slave bit 2 L2 Flash PortA slave bit 3 EMIF slave bit 4 Reserved bit 5 Cortex R5F CPU AXI slave bit 6 ACP S slave 4 4 11 Slave Error User Parity R...

Page 279: ...8 Texas Instruments Incorporated Power Management Module PMM Chapter 5 SPNU563A March 2018 Power Management Module PMM This chapter describes the power management module PMM Topic Page 5 1 Overview 28...

Page 280: ...each power domain Manages the resets to each power domain Includes failsafe compare logic to continuously monitor the states of each power domain Supports diagnostic and self test logic to validate fa...

Page 281: ...www ti com Overview 281 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Power Management Module PMM Figure 5 1 PMM Block Diagram...

Page 282: ...are turned off by the PMM Note that all I Os are in this always ON domain as well Core power domains PD2 through PD6 are controlled by the PMM PD2 contains logic related to debug instrumentation and...

Page 283: ...one power state to another will behave the same as if the power domains can be physically turned off 5 3 2 Default Power Domain State The default state of each power domain except for PD1 is controlle...

Page 284: ...nostic compare block can operate in one of four modes 5 3 7 1 Lock Step Mode This is the default mode of operation of the PSCON compare block The PSCON diagnostic compare block compares the outputs fr...

Page 285: ...block 5 3 7 5 PMM Operation During CPU Halt Debug Mode No compare errors are generated when the CPU is halted in debug mode regardless of the mode of the diagnostic compare block No status flags are u...

Page 286: ...9h Reserved Any other value Read Power domain PD2 is in Active state Write Power domain PD2 is commanded to switch to Active state 23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 LOGICPDON...

Page 287: ...N4 Reserved R 0 R WP n R 0 15 0 Reserved R 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 5 3 Logic Power Domain Control Register LOGICPDPWRCTRL1 Field...

Page 288: ..._DIS 4 Read in User and Privileged Mode returns the current value of PDCLK_DIS 4 Write in Privileged Mode only 0 Enable clocks to logic power domain PD6 1 Disable clocks to logic power domain PD6 3 PD...

Page 289: ...ser and Privileged Mode returns the current value of PDCLK_DISSET 4 Write in Privileged Mode only 0 No effect to state of clocks to power domain PD6 1 Disable clocks to logic power domain PD6 3 PDCLK_...

Page 290: ...R 4 Read in User and Privileged Mode returns the current value of PDCLK_DIS 4 Write in Privileged Mode only 0 No effect to state of clocks to power domain PD6 1 Enable clocks to logic power domain PD6...

Page 291: ...d Mode 0 Logic in power domain PD2 is in the steady Active or OFF state 1 Logic in power domain PD2 is in the process of power down up 13 17 Reserved 0 Reads return 0 Writes have no effect 16 MEM IN T...

Page 292: ...d Mode 0 Logic in power domain PD3 is in the steady Active or OFF state 1 Logic in power domain PD3 is in the process of power down up 13 17 Reserved 0 Reads return 0 Writes have no effect 16 MEM IN T...

Page 293: ...d Mode 0 Logic in power domain PD4 is in the steady Active or OFF state 1 Logic in power domain PD4 is in the process of power down up 13 17 Reserved 0 Reads return 0 Writes have no effect 16 MEM IN T...

Page 294: ...ed Mode 0 Logic in power domain PD5 is in the steady Active or OFF state 1 Logic in power domain PD5 is in the process of power down up 13 17 Reserved 0 Reads return 0 Writes have no effect 16 MEM IN...

Page 295: ...ed Mode 0 Logic in power domain PD6 is in the steady Active or OFF state 1 Logic in power domain PD6 is in the process of power down up 13 17 Reserved 0 Reads return 0 Writes have no effect 16 MEM IN...

Page 296: ...scription 31 9 Reserved 0 Reads return 0 Writes have no effect 8 PMCTRL PWRDN PMC PSCON Power Down Read in User and Privileged Mode returns current value of PMCTRL PWRDN Write in Privileged mode only...

Page 297: ...sition control sequence for logic and or SRAM 1 PMC and PSCONs for all power domains have completed generating power state transition control sequence triggered by PMC input control signals 5 4 13 PSC...

Page 298: ...pare Status Register 1 LPDDCSTAT1 Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reads return 0 Writes have no effect 20 16 LCMPE 4 0 Logic Power Domain Compare Error Each of these bi...

Page 299: ...stic Compare Status Register 2 LPDDCSTAT2 Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reads return 0 Writes have no effect 20 16 LSTET 4 0 Logic Power Domain Self test Error Type E...

Page 300: ...ISO DIAG 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 5 17 Isolation Diagnostic Status Register ISODIAGSTAT Field Descriptions Bit Field Value Description 31 5 Reserved 0 Re...

Page 301: ...2018 I O Multiplexing and Control Module IOMM This chapter describes the I O Multiplexing and Control Module IOMM Topic Page 6 1 Overview 302 6 2 Main Features of I O Multiplexing Module IOMM 302 6 3...

Page 302: ...nly n value after reset Consider the multiplexing controlled by PINMMR9 23 16 These bits control the multiplexing between the EMIF_nCS 0 RTP_DATA 15 and N2HET2 7 on the ball N17 of the 337BGA package...

Page 303: ...tached to any physical pin 6 4 Control of Multiplexed Inputs In this microcontroller some signals are connected to more than one terminal so that the inputs for these signals can come from either of t...

Page 304: ...12 2 8 RTP_DATA 06 2 9 C11 EMIF_ADDR 13 2 16 RTP_DATA 05 2 17 C12 EMIF_ADDR 14 2 24 RTP_DATA 04 2 25 11Ch C13 EMIF_ADDR 15 3 0 RTP_DATA 03 3 1 D14 EMIF_ADDR 16 3 8 RTP_DATA 02 3 9 C14 EMIF_ADDR 17 3 1...

Page 305: ...S 5 15 19 N5 ETMDATA 26 15 24 EMIF_DATA 10 15 25 N2HET2 26 15 26 150h P5 ETMDATA 27 16 0 EMIF_DATA 11 16 1 N2HET2 27 16 2 R5 ETMDATA 28 16 8 EMIF_DATA 12 16 9 N2HET2 28 16 10 GIOA 0 16 11 R6 ETMDATA 2...

Page 306: ...5 1 W6 MIBSPI5NCS 2 25 8 DMM_DATA 02 25 9 T12 MIBSPI5NCS 3 25 16 DMM_DATA 03 25 17 H18 MIBSPI5NENA 25 24 DMM_DATA 07 25 25 MII_RXD 3 25 26 ECAP5 25 29 178h J19 MIBSPI5SIMO 0 26 0 DMM_DATA 08 26 1 MII_...

Page 307: ...31 21 A4 N2HET1 16 31 24 EPWM1SYNCI 31 27 EPWM1SYNCO 31 29 190h A13 N2HET1 17 32 0 EMIF_nOE 32 1 SCI4RX 32 2 J1 N2HET1 18 32 8 EMIF_RNW 32 9 ePWM6A 32 13 B13 N2HET1 19 32 16 EMIF_nDQM 0 32 17 SCI4TX...

Page 308: ...Control of Multiplexed Inputs www ti com 308 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated I O Multiplexing and Control Module IOMM...

Page 309: ...QEP2S N A on 337ZWT PINMMR83 16 B11 PINMMR83 17 GIOA 0 A5 PINMMR83 24 R5 PINMMR83 25 260h GIOA 1 C2 PINMMR84 0 R6 PINMMR84 1 GIOA 2 C1 PINMMR84 8 B15 PINMMR84 9 GIOA 3 E1 PINMMR84 16 R7 PINMMR84 17 GI...

Page 310: ...T2 00 D6 PINMMR94 0 C1 PINMMR94 1 N2HET2 01 D8 PINMMR94 8 D4 PINMMR94 9 N2HET2 02 D7 PINMMR94 16 E1 PINMMR94 17 N2HET2 03 E2 PINMMR94 24 D5 PINMMR94 25 28Ch N2HET2 04 D13 PINMMR95 0 H3 PINMMR95 1 N2HE...

Page 311: ...ted I O Multiplexing and Control Module IOMM NOTE Inputs are broadcast to all multiplexed functions The input signals are broadcast to all modules hooked up to a terminal The application must ensure t...

Page 312: ...ate Trigger Source for Trigger Input 4 PINMMR162 24 PINMMR162 25 ADC2 Alternate Trigger Source for Trigger Input 6 39Ch PINMMR163 0 PINMMR163 1 ADC2 Alternate Trigger Source for Trigger Input 7 PINMMR...

Page 313: ...172 18 See Section 6 5 9 ePWMx Trip Zone2 TZ2n Input Filtering Select PINMMR172 24 PINMMR172 25 PINMMR172 26 ePWMx Trip Zone3 TZ3n Input Filtering Select 3C4h PINMMR173 0 PINMMR173 1 PINMMR173 2 ePWM...

Page 314: ...of Ethernet Controller Mode PINMMR160 24 is set by default This bit is used to enable the RMII Reduced Media Independent Interface of the Ethernet controller If the application desires to use the MII...

Page 315: ...WM_A1 100 5 1 0 NA NA N2HET1 12 0 1 NA NA N2HET1 17 101 6 1 0 PINMMR163 0 x PINMMR163 1 x N2HET1 14 0 1 PINMMR163 0 1 PINMMR163 1 0 N2HET1 19 0 1 PINMMR163 0 0 PINMMR163 1 1 N2HET2 1 110 7 1 0 PINMMR1...

Page 316: ...A EPWM6SOCB EPWM7SOCA EPWM7SOCB ePWM7 module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB SOCAEN SOCBEN bits inside ePWMx modules Controlled by PINMMR Control of Special Multiplexed Options www ti com 316 SPNU563A...

Page 317: ...SEL or AB B or A2 The SOCxA_SEL signals used in the above logic equations are generated using registers in the I O multiplexing module PINMMR164 0 defines the value of SOC1A_SEL This bit is set by def...

Page 318: ...the N2HET2 01 terminal By default with PINMMR179 8 1 and PINMMR179 9 0 the GIOA 5 EXTCLKIN ePWM1A terminal is selected as the input for signaling the fault condition Setting PINMMR179 8 0 and PINMMR17...

Page 319: ...O module when they are driven low Therefore the input from this terminal can optionally be connected to the GIOB 2 input This connection is enabled by setting PINMMR160 0 0 and PINMMR160 1 1 Note that...

Page 320: ...the time base clocks of all the ePWMx modules is 1 Enable the clocks to the desired individual ePWMx modules if they have been disabled 2 Set TBCLKSYNC 0 This will stop the time base clocks of any en...

Page 321: ...r using VCLK3 and then connected to the ePWM1 module s SYNCI port If PINMMR165 24 0 and PINMMR165 25 1 the SYNCI input to the ePWM1 comes from the pulse stretched N2HET1_LOO_SYNC signal 6 5 9 Control...

Page 322: ...1 PINMMR167 24 0 PINMMR167 25 1 PINMMR167 25 24 00 PINMMR167 26 1 ePWM5 PINMMR168 0 1 PINMMR168 0 0 PINMMR168 1 1 PINMMR168 1 0 00 PINMMR168 2 1 ePWM6 PINMMR168 8 1 PINMMR168 8 0 PINMMR168 9 1 PINMMR1...

Page 323: ...er Registers in the I O multiplexing module are used to control these input connections for each eQEPx module Table 6 9 Controls for eQEPx Inputs eQEPx Input Control for Double VCLK3 Synchronized Inpu...

Page 324: ...x xxx xxx xxxxxxx x x xxxxxxxx x x xxxxxxxxxxxxxx x x x x x x x x x x x x xxxxxxx xxx xxx xxx xxx xxx x x x x x xxx x x x x x xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxx x x x x x x x x x x x x xxxxxxx...

Page 325: ...is illustration the DMQREQ 32 input to the DMA module can come from several different sources including GIOA 0 By default with PINMMR175 0 1 all other sources except GIOA 0 can be selected to generate...

Page 326: ...PINMMR174 24 must be cleared to 0 Temperature sensor 1 s output is multiplexed with AD1IN 31 Temperature sensor 2 s output is multiplexed with AD2IN 31 Temperature sensor 3 s output is multiplexed wi...

Page 327: ...st write 0x83e70b13 to the kick0 register followed by a write of 0x95a4f1e0 to the kick1 register Disabling Write Access to the PINMMRs It is recommended to disable write access to the PINMMRs once th...

Page 328: ...Register Section 6 7 8 F4h FAULT_ADDRESS_REG Fault Address Register Section 6 7 9 F8h FAULT_STATUS_REG Fault Status Register Section 6 7 10 FCh FAULT_CLEAR_REG Fault Clear Register Section 6 7 11 110h...

Page 329: ...EG Boot Mode Register Offset 20h 31 16 Reserved R 0 15 1 0 Reserved ENDIAN R 0 R D LEGEND R Read only D Value read is determined by external configuration n value after reset Table 6 14 Boot Mode Regi...

Page 330: ...ons Bit Field Description 31 0 KICK0 Kicker 0 Register The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the PINMMRnn registers 6 7 4 KICK_REG1 Kic...

Page 331: ...lue after reset Table 6 17 Error Raw Status Set Register Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 writes have no effect 1 ADDR_ERR Addressing Error Status An Addre...

Page 332: ...D R W Read Write R Read only WP Write in privileged mode only n value after reset Table 6 18 Error Signaling Enabled Status Clear Register Field Descriptions Bit Field Value Description 31 2 Reserved...

Page 333: ...P 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 6 19 Error Enable Register Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return...

Page 334: ...able Clear 0 Read Addressing Error signaling is disabled Write Writing 0 has no effect 1 Read Addressing Error signaling is enabled Write Addressing Error signaling is disabled 0 PROT_ERR_EN_CLR Prote...

Page 335: ...END R Read only n value after reset Table 6 22 Fault Status Register Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reads return 0 writes have no effect 27 24 FAULT_ID Faulting Transa...

Page 336: ...is 1 Write Writing a 1 clears the current fault 6 7 12 PINMMRnn Output Pin Multiplexing Control Registers These registers control the output multiplexing of the functionality available on each pad on...

Page 337: ...24 1h Each of these byte fields control the functionality on a given ball pin Please refer to Table 6 2 for a list of multiplexed signals 23 16 PINMMRx 23 16 1h 15 8 PINMMRx 15 8 1h 7 0 PINMMRx 7 0 1...

Page 338: ...eprogrammed in the field or in the application It also allows remapping of the Flash to RAM spaces in order to save on repeated program erase cycles This chapter describes the Level 2 F021 Flash modul...

Page 339: ...specific data sheet Allows remapping of Flash to RAM spaces through Parameter Overlay Module POM For the actual size of the Flash memory for the device see the device specific data sheet 7 1 2 Defini...

Page 340: ...programming capabilities F021 Flash API Library a set of software peripheral functions to program erase the Flash module Refer to F021 Flash API Reference Guide SPNU501 for more information 7 2 Defaul...

Page 341: ...ches to any location within the Flash memory space A speculative fetch to a location with invalid ECC which is subsequently not used will not create an abort but will set the ESM flags for a correctab...

Page 342: ...x x x x x x x x x x Participating Data Bits 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 x x x x...

Page 343: ...1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0...

Page 344: ...M D D02 D24 D x4 E02 D D D15 D D35 D57 D D D51 D41 D M D D D31 x5 D D19 D09 D M D D D63 M D D D47 D D03 D25 D x6 D D20 D10 D M D D M M D D M D D04 D26 D x7 M D D M D D36 D58 D D D52 D42 D M D D M x8...

Page 345: ...by the customer but cannot be erased They are typically blank in new parts The TI OTP sectors are used to contain manufacturing information They may be read by the customer but can not be programmed...

Page 346: ...Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved All bits will be read as 0 23 16 BX_NUM_Sectors 1 32 Number of sectors in this bank 15 B7 1 1 Bank 7 is present 14 B6 0 0 Bank 6 is...

Page 347: ...ORY_SIZE R LEGEND R Read only Table 7 6 TI OTP Bank 0 Package and Memory Size Information Field Descriptions Bit Field Description 31 28 Reserved Reserved 27 16 PACKAGE Count of pins in the package 15...

Page 348: ...nsors that can be used to read the internal junction temperature on this device The temperature sensors are connected to the ADC converter See Section 6 5 13 for information on how to select the tempe...

Page 349: ...The value read from the ADC for this sensor at the third calibration temperature F008 03xAh 16 bits SxTEMP3 The temperature in degrees Kelvin F008 03xCh 16 bits 0xFFFF Reserved F008 03xEh 16 bits 0xF...

Page 350: ...wise if this requirement is met and PORRST is asserted while erasing the sector or sectors being erased will have indeterminate bits however the other sectors in the same bank and the other banks will...

Page 351: ...s Tag Error flag in the FEDAC_PxSTATUS register will be set Also refer to the device data manual for the specific error channel that will be asserted in this situation The sequence to do this test wou...

Page 352: ...5 Select the appropriate port in which the flip is desired using the DIAG_BUF_SEL bits in the FDIAGCTRL register Only legal values are 0 for port A and 4h for port B 6 Do a port A or B read to the des...

Page 353: ...of the problem The bits can then be either re programmed most common or the sector can be erased and reprogrammed 7 8 Parameter Overlay Module POM In many applications it is important to be able to ch...

Page 354: ...s to Flash while pump bank are not active Yes No No Flash Access time out Yes Yes Yes FEDAC_PxSTATUS ACC_TOUT Invalid access to L2FMC for example writes Yes No No Single bit Error during Implicit Read...

Page 355: ...ster Section 7 10 11 38h FBBUSY Flash Bank Busy Register Section 7 10 12 3Ch FBAC Flash Bank Access Control Register Section 7 10 13 40h FBPWRMODE Flash Bank Power Mode Register Section 7 10 14 44h FB...

Page 356: ...WP 1 R WP 1 LEGEND R W Read Write R Read only WP Write in Privilege Mode n value after reset Table 7 13 Flash Read Control Register FRDCNTL Field Descriptions Bit Field Value Description 31 12 Reserv...

Page 357: ...le 7 14 Read Margin Control Register FSPRD Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 RMBSEL n Read Margin Bank Select Each bit correspon...

Page 358: ...gister EE_FEDACCTRL1 offset 08h 31 16 Reserved R 0 15 6 5 4 3 0 Reserved EOCV EZCV Reserved R 0 R WP 0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in Privilege Mode n value after reset Table...

Page 359: ...timeout or parity This error is routed to the ESM Refer to the device data manual to find the group and channel on which it is routed 14 MCMD_PAR_ERR Parity Error in idle state This bit is set when a...

Page 360: ...error is routed to the ESM Refer to the device data manual to find the group and channel on which it is routed 14 MCMD_PAR_ERR Parity Error in idle state This bit is set when a parity error occurs du...

Page 361: ...peration This bit will generate an interrupt on VIM channel 61 if the FSM_EVT_EN bit of the FSM_ST_MACHINE register is set This bit must be cleared by writing a 1 to it in the interrupt routine to cle...

Page 362: ...ctor ID bits to determine which sector is disabled If the sector ID bits are not pointing to a valid sector 0 3 or the sector ID inverse bits are not an inverse of the sector ID bits then no sector is...

Page 363: ...GMODE is 0 or 7h Valid reads can occur in any mode The register clears when an address tag error is found and when leaving DIAG_MODE 5 4 0 Reserved 0 Reads return 0 Writes have no effect 7 10 9 Duplic...

Page 364: ...ction is disabled 7 10 11 Flash Bank Sector Enable Register FBSE FBSE provides one enable bit per sector for up to 16 sectors per bank Each bank in the Flash module has one FBSE register The bank is s...

Page 365: ...Reserved OTPPROTDIS 7 0 R 0 R WP 0 15 8 7 0 BAGP VREADST R WP 0 R WP Fh LEGEND R W Read Write R Read only WP Write in Privilege Mode n value after reset Table 7 25 Flash Bank Access Control Register F...

Page 366: ...LEGEND R W Read Write R Read only WP Write in Privilege Mode n value after reset Table 7 26 Flash Bank Power Mode Register FBPWRMODE Field Descriptions Bit Field Value Description 31 16 Reserved 505h...

Page 367: ...s not busy with any FSM or CPU operation 1 Bank is busy with an FSM or CPU operation 22 18 Reserved 1 Reads return 1 Writes have no effect 17 16 BANKBUSY 1 0 Bank 0 bit 16 and Bank 1 bit 17 Busy Statu...

Page 368: ...Reserved 0 Reads return 0 Writes have no effect 26 16 PSLEEP 0 7FFh Pump Sleep These bits contain the starting count value for the charge pump sleep down counter While the charge pump is in sleep mod...

Page 369: ...ons Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 2 0 BANK 0 7h Bank Enable These bits select which bank is enabled for operations such as local register access OTP...

Page 370: ...ended and set when the read verify resumes 15 RVF Read Verify Failure 1 When set indicates that a read verify mismatch is detected using the Read Verify command This bit remains set until clear_status...

Page 371: ...s command 4 CSTAT Command Status 1 Once the FSM starts any failure will set this bit When set this bit informs the host that the program erase or validate sector command failed and the command was sto...

Page 372: ...scription 31 0 EMU_DMSW This register can be written by the CPU in any mode This register is used in diagnostic mode 7 to XOR the upper 32 bits of the data being delivered to the bus master 7 10 20 EE...

Page 373: ...0 Writes have no effect 7 0 EMU_ECC 0 FFh This register can be written by the CPU in any mode This register is used in diagnostic mode 7 to XOR the ECC being delivered to the bus master 7 10 22 Flash...

Page 374: ...is bit always reads as 0 23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 DIAG_EN_KEY Diagnostic Enable Key 5h Diagnostic mode is enabled All other values Diagnostic mode is disabled 15 11...

Page 375: ...31 5 Reserved R WP u R 0 LEGEND R W Read Write R Read only WP Write in Privilege mode u Unchanged value on internal reset cleared on power up n value after reset Table 7 36 Raw Address Register FRAW_A...

Page 376: ...8 Reserved 0 Reserved 17 16 PAR_OVR_SEL Select which parity checker to invert the polarity of the parity 0 No effect 1h Idle state parity checker received inverted parity polarity 2h Command parity ch...

Page 377: ...is successful Device level settings are correct 0 RCR_VALID When the L2FMC finishes the implicit read it sets this bit to indicate that the contents of RCR_VALUE0 and RCR_VALUE1 are valid This bit wi...

Page 378: ...ed If the sector ID bits are not pointing to a valid sector 0 3 or the sector ID inverse bits are not an inverse of the sector ID bits then no sector is disabled by disable ID 3 23 22 Reserved 0 Reads...

Page 379: ...nfiguration Read Register RCR_VALUE0 Field Descriptions Bit Field Value Description 31 0 RCR_VALUE 0 Value of the lower 32 bits of the implicit read Valid only if RCR_VALID is set 7 10 30 Upper Word o...

Page 380: ...to write to any other register in the range FFF8 7200h to FFF8 72FFh This is the first register to be written when setting up the FSM All other values For all other values the FSM registers cannot be...

Page 381: ...r that is erased will be changed from 0 to 1 1 During bank erase each sector whose corresponding bit is 1 will not be erased NOTE If the bank has less than 32 sectors only those many LSB bits of FSM_S...

Page 382: ...reset Table 7 47 Flash Bank Configuration Register FCFG_BANK Field Descriptions Bit Field Value Description 31 20 EE_BANK_WIDTH 48h Bank 7 width 72 bits wide This read only value indicates the maximum...

Page 383: ...ddress Register Section 7 11 4 204h 214h POMOVLSTARTx POM Overlay Start Address Register Section 7 11 5 208h 218h POMREGSIZEx POM Region Size Register Section 7 11 6 7 11 1 POM Global Control Register...

Page 384: ...SRESP_IDLE PERR_PB PERR_PA R 0 R W1CP u R W1CP u R W1CP u 7 0 Reserved R 0 LEGEND R W Read Write R Read only W1CP Write 1 to clear in Privilege Mode u unchanged value on internal reset cleared on powe...

Page 385: ...Register POMPROGSTARTx Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reads return 0 Writes have no effect 22 6 STARTADDRESS Start address of the program memory region 5 0 Reserved 0...

Page 386: ...erlay memory region Figure 7 51 POM Region Size Register POMREGSIZEx offset 208h 218h 31 16 Reserved R 0 15 4 3 0 Reserved SIZE R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in Privilege Mode...

Page 387: ...t 2018 Texas Instruments Incorporated Level 2 RAM L2RAMW Module Chapter 8 SPNU563A March 2018 Level 2 RAM L2RAMW Module This chapter describes the Level II RAM L2RAM module Topic Page 8 1 Overview 388...

Page 388: ...dress lines and generation of correct memory selects for the RAM banks Exclusive access support Supports auto initialization of the CPU data RAM banks Supports the RAM Trace Port RTP Interface Traces...

Page 389: ...cessing ECC space Figure 8 1 RAM Memory Map 8 2 2 Safety Features The L2RAMW module incorporates some features that are designed specifically with safety considerations 8 2 2 1 ECC Handling on 8 16 an...

Page 390: ...odify write operation the results of the ECC correction are compared back again to the original data value to ensure that the SECDED logic is working correctly If an error in the SECDED logic is detec...

Page 391: ...ed on the CPU address The logic to generate these memory selects is duplicated and the outputs compared to detect any address decode errors A mismatch is indicated as an Address Error to the Error Sig...

Page 392: ...DR register is not cleared by a read in debug mode That is if a double bit error address is captured and is not read by the CPU before entering debug mode then it remains frozen during debug mode even...

Page 393: ...tialization Domain Register Section 8 3 8 44h BANK_DOMAIN_MAP0 Bank to Domain Mapping Register 0 Section 8 3 9 48h BANK_DOMAIN_MAP1 Bank to Domain Mapping Register 1 Section 8 3 10 8 3 1 L2RAMW Module...

Page 394: ...return 0 Writes have no effect 12 EEMMS Enable ESM notification Parity Redundant Address Decode SECDED malfunction for write back during memory scrubbing 0 ESM will not be signaled when an error occur...

Page 395: ...gle bit error has occurred during diagnostic of the L2RAMW SECDED logic that is used to handle read of read modify write operations This bit must be cleared by writing a 1 to it before any new error c...

Page 396: ...writing a 1 to it before any new error can be generated 0 An error did not occur 1 An error occurred 11 WEMDE Write ECC Malfunction Diagnostic Error This bit indicated an error was detected on the com...

Page 397: ...uring a CPU write operation This bit must be cleared by writing a 1 to it before any new error can be generated 0 An error did not occur 1 An error occurred 2 ADE Address Decode Error This bit indicat...

Page 398: ...mux This register is the upper 32 bits This register is used in conjunction with the RAMTEST register to perform diagnostic tests See Section 8 2 6 for details on how to start a diagnostic test 8 3 4...

Page 399: ...TOR R 0 R WP U LEGEND R W Read Write R Read only WP Write in privilege mode only U Unknown n value after reset Table 8 7 L2RAMW Diagnostic ECC Vector Register DIAG_ECC Field Descriptions Bit Field Val...

Page 400: ...he RAMERRSTATUS register are in the cleared state The trigger bit is auto clear after the test and has to be written again for a new test 7 6 TEST_MODE Test Mode This field selects either equality or...

Page 401: ...CT R WP 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 8 9 L2RAMW RAM Address Decode Vector Test Register RAMADDRDEC_VECT Field Descriptions Bit Field V...

Page 402: ...ization Domain Register MEMINIT_DOMAIN Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 MEMINIT_ENA n Memory Initialization Enable Each bit n cor...

Page 403: ...at bank 7 is associated 27 Reserved 0 Reads return 0 Writes have no effect 26 24 BANK6_MAP 0 7h This 3 bit field allows the software to read the memory power domain number that bank 6 is associated 23...

Page 404: ...bank 15 is associated 27 Reserved 0 Reads return 0 Writes have no effect 26 24 BANK14_MAP 0 7h This 3 bit field allows the software to read the memory power domain number that bank 14 is associated 2...

Page 405: ...2018 Programmable Built In Self Test PBIST Module This chapter describes the programmable built in self test PBIST controller module used for testing the on chip memories Topic Page 9 1 Overview 406 9...

Page 406: ...ROM clock speeds up to 100 MHz 9 1 2 PBIST vs Application Software Based Testing The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted specifically toward t...

Page 407: ...ed by the application s author 9 1 3 3 Memory Data Path This is the read and write data path logic between different system and peripheral memories tightly coupled to the PBIST memory interface The PB...

Page 408: ...o Y es No Y es Wait for approximately N vbus clocks Reset the PBIST controller by writing MSTGCR 0x0A Disable PBIST Test Resume PBIST self test by writing 0x02 to the STR register by writing MSTGCR 0x...

Page 409: ...all 1 s meaning all algorithms are selected Similarly program the RINFOL and RINFOU registers to indicate whether a particular RAM group in the instruction ROM would get executed or not NOTE In case...

Page 410: ...cache can be enabled for use by the CPU In addition if you are using ECC error checking scheme in the cache you must enable this by programming the CEC bits in the Auxiliary Control Register before in...

Page 411: ...the highest overall coverage The other algorithms provide additional coverage of otherwise missed boundary conditions of the SRAM operation The concept behind the general march algorithm is to indicat...

Page 412: ...ivated by first writing 1h to the PACT register Table 9 1 PBIST Registers Offset Acronym Register Description Section 160h RAMT RAM Configuration Register Section 9 5 1 164h DLR Datalogger Register Se...

Page 413: ...fy the RGS RDS values for the memory that failed the self test Figure 9 3 RAM Configuration Register RAMT offset 0160h 31 24 23 16 RGS RDS R W X R W X 15 8 7 6 5 2 1 0 DWR SMS PLS RLS R W X R W X R W...

Page 414: ...tting this bit allows the host processor to configure the PBIST controller registers 3 Reserved 1 Do not change this bit from its default value of 1 2 DLR2 ROM based testing setting this bit enables t...

Page 415: ...ing application self test Figure 9 5 PBIST Activate ROM Clock Enable Register PACT offset 0180h 31 16 Reserved R 0 15 1 0 Reserved PACT0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset...

Page 416: ...r is described in Figure 9 6 and Table 9 5 Figure 9 6 PBIST ID Register offset 184h 31 16 Reserved R 0 15 8 7 0 Reserved PBIST ID R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table...

Page 417: ...memory information available from ROM will override the RAM selection from the RAM info registers RINFOL and RINFOU OVER0 While doing ROM based testing each algorithm downloaded from the ROM has a mem...

Page 418: ...curs Figure 9 8 and Table 9 7 illustrate the FSRF0 register Figure 9 8 Fail Status Fail Register 0 FSRF0 offset 0190h 31 16 Reserved R 0 15 1 0 Reserved FSRF0 R 0 R 0 LEGEND R W Read Write R Read only...

Page 419: ...8 illustrate the FSRC0 register while Figure 9 10 and Table 9 9 illustrate the FSRC1 register Figure 9 9 Fail Status Count 0 Register FSRC0 offset 0198h 31 16 Reserved R 0 15 8 7 0 Reserved FSRC0 R 0...

Page 420: ...offset 01A0h 31 16 Reserved R 0 15 0 FSRA0 R 0 LEGEND R W Read Write R Read only n value after reset Table 9 10 Fail Status Address Register 0 FSRA0 Field Descriptions Bit Field Value Description 31 1...

Page 421: ...DL0 register while Figure 9 14 and Table 9 13 illustrate the FSRDL1 register Figure 9 13 Fail Status Data Register 0 FSRDL0 offset 01A8h 31 16 FSRDL0 R AAAAh 15 0 FSRDL0 R AAAAh LEGEND R W Read Write...

Page 422: ...n be programmed according to Table 9 14 Figure 9 15 ROM Mask Register ROM offset 01C0h 31 16 Reserved R 0 15 2 1 0 Reserved ROM R 0 R W 3h LEGEND R W Read Write R Read only n value after reset Table 9...

Page 423: ...trate this register Figure 9 16 ROM Algorithm Mask Register ALGO offset 01C4h 31 24 23 16 ALGO3 ALGO2 R W FFh R W FFh 15 8 7 0 ALGO1 ALGO0 R W FFh R W FFh LEGEND R W Read Write R Read only n value aft...

Page 424: ...re 9 17 and Table 9 16 illustrate this register The information from this register is used only when bit 0 in OVER register is not set Figure 9 17 RAM Info Mask Lower Register RINFOL offset 01C8h 31 2...

Page 425: ...egister is all 1s which means all the RAM Info Groups would be selected Figure 9 18 and Table 9 17 illustrate this register Figure 9 18 RAM Info Mask Upper Register RINFOU offset 01CCh 31 24 23 16 RIN...

Page 426: ...emory self test OVER 0x0 7 Select the Algorithm refer to Table 2 6 ALGO 0x00000004 Algo 3 March13N for two port DCAN1 RAM 8 Program the RAM group Info to select DCAN1 DCAN1 RAM is Group 3 refer to Tab...

Page 427: ...e run refer to Table 2 6 ALGO 0x0000000C select March13N for single port and two port RAMs 8 Select both Algorithm and RAM information from on chip PBIST ROM ROM 0x3 9 Configure PBIST to run in ROM Mo...

Page 428: ...the on chip self test controller STC modules Topic Page 10 1 General Description 429 10 2 STC Module Assignments 436 10 3 STC Programmers Flow 437 10 4 Application Self Test Flow 438 10 5 STC1 Segmen...

Page 429: ...dundant logic cores are tested in parallel with the same patterns but have a dedicated signature generator This is used in the safety critical redundant logic that runs in lock step Figure 10 2 and Fi...

Page 430: ...edundant Cortex R5F CPUs and SCU and another one for the nHET modules Each STC module comprises of the same basic blocks and has same features and functionality The STC module is composed of following...

Page 431: ...ti com General Description 431 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Self Test Controller STC Module 10 1 3 3 Peripheral Bus VBUSP Interface...

Page 432: ...Interface VBUSP Inteface Test Controller DBIST CNTRL2 Compare DBIST CNTRL1 CPU1 Cortex R5F Bisted CORE CPU2 Cortex R5F Bisted CORE General Description www ti com 432 SPNU563A March 2018 Submit Docume...

Page 433: ...C REG BLOCK STC_BYPASS ATE Interface VBUSP Inteface Test Controller DBIST CNTRL2 DBIST CNTRL1 nHET1 nHET2 misr_out www ti com General Description 433 SPNU563A March 2018 Submit Documentation Feedback...

Page 434: ...TRL2 CCM R5F DBIST CNTRL1 CPU1 Cortex R5F Bisted CORE CPU2 Bisted CORE Cortex R5F General Description www ti com 434 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments...

Page 435: ...TRL2 CCM R5F DBIST CNTRL1 CPU1 Cortex R5F Bisted CORE CPU2 Cortex R5F Bisted CORE www ti com General Description 435 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments...

Page 436: ...on the redundant CPUs and SCU STC2 is used for running self test on the two nHET modules The two instances are independent of each other Table 10 1 STC Module Assignments Module Segments Targeted IP...

Page 437: ...gisters for clock division ratio of the source clock for each segment Number of intervals for the run and interval start type restart continue from previous interval preload Program the time out count...

Page 438: ...CPU STC generates a CPU reset after completion of each test regardless of pass or fail You can run the STC test during startup or can divide STC into subsets of 1 or more intervals and executed durin...

Page 439: ...STC This is compared with the golden MISR value stored in the ROM At the end of a CPU self test the STC controller updates the status flags in the Global Status Register STCGSTAT and resets the CPU In...

Page 440: ...ports of DBIT Read the MISR value into STC from the dbist to compare with Golden MISR The STC enable forces the CPU bus to idle transaction mode Is Self Test Enabled All patterns completed End of Self...

Page 441: ...es 0 0 0 1 56 85 1629 2 64 19 3258 3 68 76 4887 4 71 99 6516 5 75 00 8145 6 76 61 9774 7 78 08 11403 8 79 20 13032 9 80 18 14661 10 81 03 16290 11 81 90 17919 12 82 58 19548 13 83 24 21177 14 83 73 22...

Page 442: ...52 91 35 84708 53 91 42 86337 54 91 52 87966 55 91 63 89595 56 91 73 91224 57 91 81 92853 58 91 89 94482 59 91 97 96111 60 92 05 97740 61 92 11 99369 62 92 17 100998 63 92 24 102627 64 92 31 104256 65...

Page 443: ...68 172674 107 94 72 174303 108 94 78 175932 109 94 82 177561 110 94 86 179190 111 94 91 180819 112 94 95 182448 113 94 99 184077 114 95 04 185706 115 95 08 187335 116 95 15 188964 117 95 19 190593 11...

Page 444: ...of intervals to be run based on the coverage needed and allowed time for STC execution Table 10 5 Typical Execution Times for STC1 Segment 1 Number of Intervals Coverage GCLK1 330 MHz STCCLK 110 MHz G...

Page 445: ...05 38 95 54 51870 39 95 66 53235 40 95 69 54600 41 95 75 55965 42 95 79 57330 43 95 82 58695 44 95 85 60060 45 95 91 61425 46 95 95 62790 47 95 99 64155 48 96 01 65520 49 96 04 66885 50 96 07 68250 51...

Page 446: ...Register Section 10 8 3 0Ch STCCADDR1 STC Current ROM Address Register CORE1 Section 10 8 4 10h STCCICR STC Current Interval Count Register Section 10 8 5 14h STCGSTAT Self Test Global Status Register...

Page 447: ...STC Global Control Register 0 STCGCR0 Field Descriptions Bit Field Value Description 31 16 INTCOUNT Number of intervals of self test run 0 FFFFh This register specifies the number of intervals to run...

Page 448: ...7 4 3 0 Reserved SEG0_CORE_SEL Reserved STC_ENA R 0 R WP 0 R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privilege mode only n value after nPORST power on reset or System reset Table 10 1...

Page 449: ...d Write WP Write in privilege mode only n value after nPORST power on reset or System reset Table 10 11 Self Test Run Timeout Counter Preload Register STCTPR Bit Field Description 31 0 RTOD Self test...

Page 450: ...M address address or micro code load accessed during self test Segment0 Core1 and other segments This is the current value of the STC program counter 10 8 5 STC Current Interval Count Register STCCICR...

Page 451: ...W1CP Write 1 to clear in privilege mode n value after reset Table 10 14 Self Test Global Status Register STCGSTAT Field Descriptions Bit Field Value Description 31 12 Reserved 0 Reads return 0 Writes...

Page 452: ...ents will not be run FSEG_ID bits in this register indicate which segment failed Figure 10 14 Self Test Fail Status Register STCFSTAT offset 18h 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved FSEG_ID TO_E...

Page 453: ...CORE1 Current MISR Register CORE1_CURMISR2 offset 20h 31 16 MISR 63 48 R 0 15 0 MISR 47 32 R 0 LEGEND R Read only n value after reset Figure 10 17 CORE1 Current MISR Register CORE1_CURMISR1 offset 24h...

Page 454: ...gure 10 20 CORE2 Current MISR Register CORE2_CURMISR2 offset 30h 31 16 MISR 63 48 R 0 15 0 MISR 47 32 R 0 LEGEND R Read only n value after reset Figure 10 21 CORE2 Current MISR Register CORE2_CURMISR1...

Page 455: ...t Table 10 18 Signature Compare Self Check Regsiter STCSCSCR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reads return 0 Writes have no effect 4 FAULT_INS Enable fault insertion 0 No...

Page 456: ...tware compatibility NOTE The clock divider ratio is applied when the corresponding segment is under test Figure 10 25 STC Clock Prescalar Register STCCLKDIV offset 44h 31 27 26 24 23 19 18 16 Reserved...

Page 457: ...ter before the test is started Figure 10 26 Segment Interval Preload Register STCSEGPLR offset 48h 31 16 Reserved R 0 15 2 1 0 Reserved SEGID_PLOAD R 0 RWP 0 LEGEND R W Read Write R Read only WP Write...

Page 458: ...r depending on the number of intervals selected STCGCR0 31 16 40 4 Configure self test run time out counter preload register STCTPR 31 0 0xFFFFFFFF 5 Optionally configure SEG0_CORE_SEL bits in registe...

Page 459: ...the CORE1_FAIL or CORE2_FAIL bits would be set Step 3 Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register Then restart the self test by programming bit 0 of the STCGC...

Page 460: ...nts Incorporated System Memory Protection Unit NMPU Chapter 11 SPNU563A March 2018 System Memory Protection Unit NMPU This chapter describes the System Memory Protection Unit NMPU Topic Page 11 1 Over...

Page 461: ...but a subset of the host CPUs own memory protection unit Provide protection to memory regions ranging from 32 bytes to 4GB in size Up to 8 memory protection regions Note that the number of memory regi...

Page 462: ...tput Bus Interconnect Interface Priority Mux Priority Mux fail control Diag mode Int addr Error Overview www ti com 462 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instrumen...

Page 463: ...and allows you to enable the region MPUREGACR MPU region access control register It defines the MPU region accessing permission for user or privilege mode NMPU has one region register that you have t...

Page 464: ...Yes No No No No Update ERRSTAT and ERRADDR Set BGERR Redirect Access to NULL Slave Update ERRSTAT and ERRADDR Set APERR Redirect Access to NULL Slave No No No Bus Output to Interconnect Yes Yes Yes H...

Page 465: ...ESM if ERRENA Ah are generated for accesses that violate the access permissions This diagnostic mode is useful to test the full signal chain from bus master access generation logic to NMPU comparator...

Page 466: ...rrection cycle 11 3 How to Use NMPU 11 3 1 How to Use NMPU in Functional Mode The NMPU is used to configure the bus master MPU region in such a way that the bus master does not interfere with the memo...

Page 467: ...d not sending any transaction Please follow the bus master TRM on how to idle the bus interface it will be different from one bus master to another 2 Write 0xA to unlocked field LOCK of MPULOCK regist...

Page 468: ...ansient fault or permanent fault If DIAGERR safety diagnostic error bit is set and ERRFLAG is also set this indicates that the 1oo1D diagnostic architect for input address masking address translation...

Page 469: ...e different from one bus master to another 2 Unlock the MPU registers by writing 0xA to LOCK field of MPULOCK register 3 Disable memory protection by writing 0x5 to MPUENA key of MPUCTRL1 register 4 P...

Page 470: ...ters by writing 0xA to LOCK field of MPULOCK register 3 Disable memory protection by writing 0x5 to MPUENA field of MPUCTRL1 register 4 Program the different MPU regions in MPUREGBASE0 7 MPUREGSENA0 7...

Page 471: ...en for such an access Writes to registers other than MPUERRSTAT register are ignored when NMPU registers are locked LOCK 5h in MPULOCK register No error response is given for such an access Table 11 3...

Page 472: ...INOR 0 Minor revision number 11 4 2 MPU Lock Register MPULOCK Figure 11 5 MPU Lock Register MPULOCK offset 04h 31 16 Reserved R 0 15 4 3 0 Reserved LOCK R 0 R WP 0 LEGEND R W Read Write R Read only WP...

Page 473: ...rnal diagnostic mode Read Returns the current value of R_W Write in Privilege 0 For access permission checks treat the transaction as read 1 For access permission checks treat the transaction as write...

Page 474: ...y W1CP Write 1 to clear in privilege mode only n value after reset Table 11 8 MPU Error Status Register MPUERRSTAT Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reserved Reads return...

Page 475: ...s permission violation in region 0 1h MPU compare fail generated because of access permission violation in region 1 2h MPU compare fail generated because of access permission violation in region 2 3h...

Page 476: ...ites have no effect Shows the address for the first transaction that resulted in a compare fail 11 4 7 MPU Control Register 1 MPUCTRL1 Figure 11 10 MPU Control Register 1 MPUCTRL1 offset 20h 31 16 Res...

Page 477: ...Description 31 4 Reserved 0 Reserved Reads return 0 3 0 ERRENA MPU Error Pulse Enable This is the key for enabling ERROR pulse output generation for the Error Signaling Module This field is updated on...

Page 478: ...ion defined Table 11 12 MPU Type Register MPUTYPE Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved Reads return 0 15 8 NUMREG Number of MPU Regions Indicates the number of impl...

Page 479: ...ld Descriptions Bit Field Value Description 3 0 BASE_ADDRESS Base address Defines the base address for an MPU region Read Returns current value of base address Write in Privilege Defines the base addr...

Page 480: ...current value of REG_SIZE Write in Privilege Defines the size of an MPU region 0 3h Reserved 4h 32 bytes 5h 64 bytes 6h 128 bytes 7h 256 bytes 8h 512 bytes 9h 1 KB Ah 2 KB Bh 4 KB Ch 8 KB Dh 16 KB Eh...

Page 481: ...0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 11 15 MPU Region Access Control Register MPUREGACR Field Descriptions Bit Field Value Descrip...

Page 482: ...Read only WP Write in privileged mode only n value after reset Table 11 16 MPU Region Number Register MPUREGNUM Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved Reads return 0 3...

Page 483: ...Error Profiling Controller EPC Chapter 12 SPNU563A March 2018 Error Profiling Controller EPC This chapter describes overall functionality and how to use the Error Profiling Controller EPC Topic Page...

Page 484: ...as IP The Error Profiling Module section in the Architecture chapter indicates which IP correctable and uncorrectable event are hooked up to EPC Each IP can provide either or both correctable and unco...

Page 485: ...trigger correctable fault event to EPC The EPC provides a 4 entry FIFO to each of these IP s to capture correctable event and its 64 bit aligned addresses A FIFO full condition happens when all 4 entr...

Page 486: ...n functional mode CPU can only set CAM index to available state but not occupied state Occupied state setting by CPU will be ignored CPU can also update the CAM content In this case once the CAM conte...

Page 487: ...o determine if this is CAM or FIFO overflow or a registration of new correctable fault event in CAM a If it is FIFO overflow the OVRFLWSTAT indicates which IP FIFO has overflow so you can make decisio...

Page 488: ...sed through the system module register space in the Cortex R5F CPUs memory map All registers are 32 bit wide and are located on a 32 bit boundary Reads and writes to registers are supported in 8 16 an...

Page 489: ...5 11 10 8 7 6 5 0 RTL MAJOR CUSTOM MINOR R 0 R 0 R 0 R 0 LEGEND R Read only n value after synchronous reset on system reset Table 12 2 EPC REVID Register EPCREVID Field Descriptions Bit Field Value De...

Page 490: ...ic enable key These bits when enabled allow the CPU to access the CAM content to clear or set any entry CAM index or write any pattern to CAM content Internal RTL will implement self correction logic...

Page 491: ...d Reads return 0 1 0 UEn Uncorrectable ECC Fault Status Bit for interface n Each bit corresponds to one uncorrectable EPC IP interface If the IP triggers uncorrectable error one of these bits gets set...

Page 492: ...ptions Bit Field Value Description 31 3 Reserved 0 Reserved Reads return 0 2 CAM_FULL CAM full status bit This bit is set when CAM has no more available index available to accept new correctable addre...

Page 493: ...ous reset by power on reset Table 12 6 FIFO Full Status Register FIFOFULLSTAT Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved Reads return 0 4 0 FULLn FIFO interface n is full...

Page 494: ...occurs this bit is set If any of these bits is set and the FIFO overflow interrupt enable bit is set EPC triggers FIFO overflow interrupt The number of implemented bits depends on the number of implem...

Page 495: ...ccess is non intrusive not unfreeze Power on reset write clear to the corresponding UERRSTAT bit or reading of the ERRADDR register also unfreezes this register for each interface Unfreeze means that...

Page 496: ...field in the entry valid tags registers CAM_INDEXn The index has a self correction mechanism as follows Key active if valid key 1010 or 1011 or 1000 or 1110 or 0010 Key inactive if valid key 0101 or...

Page 497: ...in lockstep to detect faults that may result in unsafe operating conditions The CCM R5F detects faults and signals them to an error signaling module ESM NOTE In general the R5F term is used when refe...

Page 498: ...ould only go through the main CPU Any signals which indicate activity will be flagged as an error The second feature is the Power Domain PD Inactivity Monitor Similar to the Checker CPU Inactivity Mon...

Page 499: ...cribed in Section 13 1 there are four different run time diagnostics supported by the CCM R5F The CCM R5F compares the core bus outputs of the master and checker Cortex R5F CPUs on the microcontroller...

Page 500: ...and CCM R5F VIM compare respectively CPU types of output signals to be compared Global signals Interrupt signals All L1 cache interface signals All cache coherency signals All L1 TCM interface signal...

Page 501: ...and clocked for one cycle The duration of self test for CPU Output Compare Diagnostic is 4947 CPU clock cycles GCLK1 and 151 system peripheral clock cycles VCLK for VIM Output Compare Diagnostic NOTE...

Page 502: ...is repeated until every single signal position is verified on both CPU signal ports The Compare Mismatch Test is terminated if the CCM R5F reports a compare match versus the expected compare mismatch...

Page 503: ...or one clock cycle After that the mode is automatically switched to lockstep mode The key register MKEY1 for CPU output compare and MKEY2 for VIM output compare will indicate the lockstep key mode onc...

Page 504: ...all zeros The resultant values of the 8 signals after the XOR logic with the POLARITYINVERT register will still be the same as the original 8 signal values However by programming the POLARITYINVERT t...

Page 505: ...es address and control are valid on the Checker CPU s AXI peripheral port for read transaction BVALIDS When asserted indicates that a valid write response is available on the Checker CPU s AXI slave p...

Page 506: ...until every inactivity monitor signal position is verified on the checker CPU Table 13 6 shows the sequence of Compare Mismatch Test There is no error signal sent to ESM if the expected errors are se...

Page 507: ...ag CCM R5F Power Domain Monitor Failure In addition the corresponding bus masters for which the compare block detected the monitor failure are also captured in the CCMPDSTAT0 register Self test mode E...

Page 508: ...s the bit unchanged 1 Read CPU signal compare mismatch Write Clears the bit 15 9 Reserved Reads return 0 Writes have no effect 8 STC1 Self test Complete for CPU Output Compare Diagnostic Note This bit...

Page 509: ...escriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0 Writes have no effect 3 0 MKEY1 Mode Key to select operation for CPU Output Compare Diagnostic Read in User and Privileged mode W...

Page 510: ...lears the bit 15 9 Reserved Reads return 0 Writes have no effect 8 STC2 Self test Complete for VIM Output Compare Diagnostic Note This bit is always 0 when not in self test mode Once set switching fro...

Page 511: ...escriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0 Writes have no effect 3 0 MKEY2 Mode Key to select operation for VIM Output Compare Diagnostic Read in User and Privileged mode W...

Page 512: ...ears the bit 15 9 Reserved Reads return 0 Writes have no effect 8 STC3 Self test Complete for Checker CPU Inactivity Monitor Note This bit is always 0 when not in self test mode Once set switching fro...

Page 513: ...elf test mode 9h Read Returns current value of the MKEY3 Write Error Forcing mode Fh Read Returns current value of the MKEY3 Write Self test Error Forcing mode Other values Note It is recommended to n...

Page 514: ...ears the bit 15 9 Reserved Reads return 0 Writes have no effect 8 STC4 Self test Complete for Power Domain Inactivity Monitor Note This bit is always 0 when not in self test mode Once set switching fr...

Page 515: ...escriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0 Writes have no effect 3 0 MKEY4 Mode Key to select operation for Power Domain Inactivity Monitor Read in User and Privileged mode...

Page 516: ...ion on the master when the power domain is turned off Write Writes have no effect Any non zero value Read An unexpected bus transaction is detected on the master Write Writes have no effect 3 2 HTU2_T...

Page 517: ...Oscillator and PLL This chapter describes the oscillator and PLL clock source paths for the device Topic Page 14 1 Introduction 518 14 2 Quick Start 519 14 3 Oscillator 520 14 4 Low Power Oscillator a...

Page 518: ...an can be conveniently achieved with an external crystal or resonator Additionally the PLL allows the flexibility to be able to synthesize one of multiple frequency options from a given crystal or res...

Page 519: ...rge valid window for the clock detect in order to refine the clock detect window the low power oscillator can be trimmed The initial trim value is stored in one time programmable section of the flash...

Page 520: ...the crystal resonator removes distortion from the OSCOUT waveform leaving a sinusoidal input waveform NOTE Vendor Validation of Resonators Crystals The crystal is a very tight bandpass filter while a...

Page 521: ...ngs at a high enough amplitude to pass an input clock into the core domain and nPORRST is released 1024 oscillator periods are counted before setting the CLKSR0V bit in the Clock Source Valid Status R...

Page 522: ...omparator to independently trim the HF LPO and LF LPO frequencies BIAS ENABLE LPOMONCTL 24 enables disables the current source which drives the LPO 14 4 1 Clock Detect The LPO HF clock frequency is ty...

Page 523: ...rol Registers 3 Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register CSDISSET This action resets the clock detect and allows the oscillator to propagate throu...

Page 524: ...r allows the user to clear CSDIS bits without using a read modify write code construct 14 4 5 3 Disable LPO Current Bias The LPO current source may be disabled after the clock detect is disabled and H...

Page 525: ...LL divides the reference input for a lower frequency input into the PLL fINTCLK fCLKIN NR The PLL multiplies this internal frequency by NF to get the VCO output clock frequency fOutput CLK fINTCLK NF...

Page 526: ...bit field causes the PLL CLK to be gated these changes to ODPLL should be completed before configuring a clock domain for an asynchronous clock source Some clock domains RTICLK1 VCLK2 require a freque...

Page 527: ...modulation waveform is triangular and should be enabled after lock The modulation is digital and the spreading profile is triangular down spread which implies the modulation waveform is composed of a...

Page 528: ...LID signal is dependent upon the PLL Slip signals so that VALID cannot be set if either slip signal is active PLL Clock The PLL output clock runs at the programmed frequency When enabled it takes some...

Page 529: ...it field causes the PLL CLK to be gated these changes to ODPLL should be completed before configuring a clock domain for an asynchronous clock source Some clock domains RTICLK1 VCLK2 require a frequen...

Page 530: ...RRST 0 1 that release is delayed by 1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted The system reset release is delayed by an additional 8 oscillator cl...

Page 531: ...the flexibility of the PLL s response to failure The slip filtering circuit samples the slip based on HF LPO The filter defines the number of consecutive HF LPO cycles for which the slip signal must...

Page 532: ...cleared if it was previously set 4 Re enable PLL1 by setting the appropriate bit in the Clock Source Disable Clear Register CSDISCLR 5 Switch the clock domains back to PLL1 If PLL2 fails the PLL s sli...

Page 533: ...re cleared by the COUNTER_RESET 3 Set COUNTER_EN and clear COUNTER_RESET This step releases the reset and enables the counter to begin counting 4 After a wait loop poll for COUNTER_READ_READY to set A...

Page 534: ...the System and Peripheral Control Registers The following sections describe the two PLL registers used in the system module These registers support 8 16 and 32 bit write accesses The reset values for...

Page 535: ...ould be set equal to NR 7 Reserved 0 Reads return 0 Writes have no effect 6 COUNTER_READ_READY Counter read ready Indicates that SSW_CAPTURE_COUNT SSWPLL2 and SSW_CLKOUT_COUNT SSWPLL3 can be read 0 Co...

Page 536: ...Bit 24 of CLKOUT counter is selected 5h Bit 26 of CLKOUT counter is selected 6h Bit 28 of CLKOUT counter is selected 7h Bit 30 of CLKOUT counter is selected 0 EXT_COUNTER_EN Measurement mode 0 Modulat...

Page 537: ...WPLL3 register is shown in Figure 14 8 and described in Table 14 8 This register applies to PLL1 but does not apply to PLL2 Figure 14 8 SSW PLL BIST Control Register 3 SSWPLL3 offset 2Ch 31 16 SSW_CLK...

Page 538: ...ustrates the sub blocks in a basic PLL circuit The VCO adjusts its frequency until the two signals into the PFD have the same phase and frequency The feedback path from VCO to PFD divides the frequenc...

Page 539: ...0 and 101 in equal proportions in this case the PLLMUL bit field would be programmed as 99 5 0x6380 This fractional multiplication is useful when trying to achieve final frequencies that are non integ...

Page 540: ...m process devices can be used without modification Suppose that using a 20 MHz crystal the application requires 180 MHz GCLK1 and HCLK frequency 100 kHz spreading frequency 0 5 spreading depth 1 Choos...

Page 541: ...plier offset equal to 19 If using MULMOD 8 0 then 20 21 MULMOD will be set to 115 7 Convert the PLL parameters into bit field values NR 5 implies that REFCLKDIV 5 0 4 NS 20 implies that SPRATE 8 0 19...

Page 542: ...al Clock Comparator DCC Module Chapter 15 SPNU563A March 2018 Dual Clock Comparator DCC Module This chapter describes the dual clock comparator DCC module Topic Page 15 1 Introduction 543 15 2 Module...

Page 543: ...e used to ensure the correct frequency range for several different device clock sources thereby enhancing the system safety metrics 15 1 1 Main Features The main features of each of the DCC modules ar...

Page 544: ...he actual frequencies of clock0 and clock1 are equal to their expected frequencies then the counter1 will reach zero either at the same time as counter0 or during the count down of the valid0 counter...

Page 545: ...window otherwise signal an error reload Count0 Count1 Error no error 0 0 Count1 Count0 Valid0 www ti com Module Operation 545 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas In...

Page 546: ...k0 reload Count0 Counter1 reaches 0 before Clock1 Valid0 Error Counter0 reaches 0 Count1 0 0 Module Operation www ti com 546 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Inst...

Page 547: ...ource 5 using the main oscillator as a reference This measurement sequence would proceed as follows The application sets up the seed values for counter0 and valid0 for the duration of the measurement...

Page 548: ...an expected It includes the case when clock1 is stuck at 1 or 0 Any error freezes the counters from counting An application may then read out the counter values to help determine what caused the error...

Page 549: ...Table 15 1 DCC Control Registers Offset Acronym Register Description Section 00h DCCGCTRL DCC Global Control Register Section 15 4 1 04h DCCREV DCC Revision Id Register Section 15 4 2 08h DCCCNT0SEED...

Page 550: ...Others DONE interrupt is generated when the DONE flag is set in the DCC Status DCCSTAT register 11 8 SINGLE SHOT Single Shot Mode Enable Any operation mode read privileged mode write Ah DCC stops cou...

Page 551: ...fect 10 8 MAJOR 2h Major revision number Reads return 0x2 writes have no effect 7 6 CUSTOM 0 Custom version number Reads return 0x0 writes have no effect 5 0 MINOR 4h Minor revision number Reads retur...

Page 552: ...mode only sets the current seed value for Valid0 Writes in user mode are ignored NOTE Seed for Valid0 must be at least 0x4 The DCC must only be enabled after programming a value greater than or equal...

Page 553: ...only n value after reset Table 15 7 DCC Status Register DCCSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect 1 DONE Single Shot Sequence Done fla...

Page 554: ...et 18h 31 20 19 16 Reserved COUNT0 R 0 R 0 15 0 COUNT0 R 0 LEGEND R Read only n value after reset Table 15 8 DCC Counter0 Value Register DCCCNT0 Field Descriptions Bit Field Value Description 31 20 Re...

Page 555: ...may not return exact current value of Valid0 Reading the Valid0 value while counting is enabled may not return the exact value of the Valid0 15 4 9 DCC Counter1 Value Register DCCCNT1 Figure 15 15 and...

Page 556: ...effect 15 12 KEY Key to enable clock source selection for counter1 Reads in any operating mode return the current value of the key Writes in privileged mode set the key value Ah Writing Ah as the key...

Page 557: ...0CLKSRC offset 28h 31 16 Reserved R 0 15 4 3 0 Reserved CNT0 CLKSRC R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 15 12 DCC Counter0 Clock So...

Page 558: ...63A March 2018 Error Signaling Module ESM This chapter provides the details of the error signaling module ESM that aggregates device errors and provides internal and external error response based on e...

Page 559: ...n behavior 32 Group3 high severity channels with no interrupt generation and predefined ERROR pin behavior These channels have no interrupt response as they are reserved for CPU based diagnostics that...

Page 560: ...7 ESMILSR7 ESMILCR7 Overview www ti com 560 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Error Signaling Module ESM Table 16 1 ESM Interrupt and ERRO...

Page 561: ...SR7 ESMSR2 and ESMSR3 to debug the error If an RST is triggered or the error interrupt has been served the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cle...

Page 562: ...the ERROR pin can be calculated as 22 Once this period expires the ERROR pin is set to high in case the reset of the ERROR pin was requested This request is done by writing an appropriate key 0x5 to t...

Page 563: ...nctionality By writing a dedicated key to the error forcing key register ESMEKR the ERROR pin is set to low for the specified time The following steps describe how to force an error condition 1 Check...

Page 564: ...4 ESMIESR4 and ESMIECR4 ESMIEPSR7 ESMIEPCR7 ESMIESR7 and ESMIECR7 ERROR Recommended Programming Procedure www ti com 564 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instrume...

Page 565: ...rrupt Offset High Register Section 16 4 11 2Ch ESMIOFFLR ESM Interrupt Offset Low Register Section 16 4 12 30h ESMLTCR ESM Low Time Counter Register Section 16 4 13 34h ESMLTCPR ESM Low Time Counter P...

Page 566: ...ister unchanged 1 Read Failure on channel x has influence on ERROR pin Write Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register 16 4 2 ESM Disable ER...

Page 567: ...the corresponding clear bit in the ESMIECR1 register unchanged 1 Read Interrupt is enabled Write Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register 16 4 4 ESM Interrupt En...

Page 568: ...of channel x is mapped to high level interrupt line Write Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register 16 4 6 ESM Interrupt L...

Page 569: ...rite Leaves the bit unchanged 1 Read Error occurred interrupt is pending Write Clears the bit Note After RST if one of these flags are set and the corresponding interrupt are enabled the interrupt ser...

Page 570: ...ad No error occurred Write Leaves the bit unchanged 1 Read Error occurred Write Clears the bit 16 4 10 ESM ERROR Pin Status Register ESMEPSR Figure 16 20 ESM ERROR Pin Status Register ESMEPSR offset 2...

Page 571: ...higher priority than interrupts of error Group1 Inside a group channel 0 has highest priority and channel 31 has lowest priority User and privileged mode read Returns number of pending interrupt with...

Page 572: ...t request for the low level interrupt line Inside a group channel 0 has highest priority and channel 31 has lowest priority User and privileged mode read Returns number of pending interrupt with the h...

Page 573: ...s triggered by the peripheral clock VCLK Note Low time counter is set to the default pre load value of the ESMLTCPR in the following cases 1 Reset power on reset or warm reset 2 An error occurs 3 User...

Page 574: ...ROR pin set to high when the low time counter LTC has completed then the EKEY bit will switch back to normal mode EKEY 0000 Ah Forces error on ERROR pin All other values Activates normal mode 16 4 16...

Page 575: ...r unchanged 1 Read Failure on channel x has influence on ERROR pin Write Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register 16 4 18 ESM Influence ERR...

Page 576: ...e corresponding clear bit in the ESMIECR4 register unchanged 1 Read Interrupt is enabled Write Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register 16 4 20 ESM Interrupt Ena...

Page 577: ...pt of channel x is mapped to high level interrupt line Write Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register 16 4 22 ESM Interrup...

Page 578: ...1 to clear in privilege mode only n value after reset PORRST X value is unchanged Table 16 25 ESM Status Register 4 ESMSR4 Field Descriptions Bit Field Value Description 63 32 ESF Error Status Flag P...

Page 579: ...r unchanged 1 Read Failure on channel x has influence on ERROR pin Write Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register 16 4 25 ESM Influence ERR...

Page 580: ...e corresponding clear bit in the ESMIECR7 register unchanged 1 Read Interrupt is enabled Write Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register 16 4 27 ESM Interrupt Ena...

Page 581: ...pt of channel x is mapped to high level interrupt line Write Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register 16 4 29 ESM Interrup...

Page 582: ...1 to clear in privilege mode only n value after reset PORRST X value is unchanged Table 16 32 ESM Status Register 7 ESMSR7 Field Descriptions Bit Field Value Description 95 64 ESF Error Status Flag P...

Page 583: ...an operating system timer to support a real time operating system RTOS NOTE This chapter describes a superset implementation of the RTI module that includes features and functionality related to DMA F...

Page 584: ...ay bus with an automatic switch to an internally generated timebase when a failure with the FlexRay timebase is detected 17 1 1 Features The RTI module has the following features Two independent 64 bi...

Page 585: ...ters can be programmed to be compared to either counter block 0 or counter block 1 The following sections describe the individual functions in more detail Figure 17 1 RTI Block Diagram 17 2 1 Counter...

Page 586: ...l 31 0 Up Counter Register RTIUC0 31 0 31 0 RTICLK 31 0 31 0 31 0 OVLINT1 To Compare Unit Compare Up Counter RTICPUC1 Up Counter Capture Up Counter RTICAUC1 Free Running Counter RTIFRC1 Capture Free R...

Page 587: ...r register RTICAUCx which then holds the value captured at the time when reading the capture free running counter register RTICAFRCx NOTE The capture up counter registers are implemented as shadow reg...

Page 588: ...to avoid missing operating system ticks 17 2 4 Synchronizing Timer Events to Network Time NTU For applications which are participating on a time triggered communication bus it is often beneficial to s...

Page 589: ...has to be set higher than 0 and lower than the timebase low compare value This effectively opens a window in which an edge of the NTUx signal is expected see Figure 17 5 Outside this window no edges...

Page 590: ...mebase high compare are programmed to a valid state before switching TBEXT to an external source This state is necessary to allow the timebase control circuit to operate correctly The following condit...

Page 591: ...www ti com Module Operation 591 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Real Time Interrupt RTI Module Figure 17 7 Missing NTUx Signal Example 1...

Page 592: ...counter will be decremented with the RTICLK frequency Figure 17 9 DWD Operation The expiration time of the DWD down counter can be determined with the following equation texp DWDPRLD 1 213 RTICLK wher...

Page 593: ...igital Watchdog DWD preload register RTIDWDPRLD setting to define the end time of the window The start time of the window is defined by a window size configuration register RTIWWDSIZECTRL The default...

Page 594: ...g events while in Sleep mode is not supported as the clock to the RTI is not active When the device is put into low power mode the peripheral which is generating the external clock NTU is no longer ac...

Page 595: ...ounter 1 Register Section 17 3 14 50h RTICOMP0 RTI Compare 0 Register Section 17 3 15 54h RTIUDCP0 RTI Update Compare 0 Register Section 17 3 16 58h RTICOMP1 RTI Compare 1 Register Section 17 3 17 5Ch...

Page 596: ...USEL Select NTU signal These bits determine which NTU input signal is used as external timebase 0h NTU0 5h NTU1 Ah NTU2 Fh NTU3 All other values Tied to 0 15 COS Continue on suspend This bit determine...

Page 597: ...scriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect 1 INC Increment free running counter 0 This bit determines whether the free running counter 0 RTIFRC0 is aut...

Page 598: ...Write in privileged mode only n value after reset Table 17 4 RTI Capture Control Register RTICAPCTRL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect...

Page 599: ...ffect 12 COMPSEL3 Compare select 3 This bit determines the counter with which the compare value held in compare register 3 RTICOMP3 is compared 0 Value will be compared with RTIFRC0 1 Value will be co...

Page 600: ...r RTIUC0 The up counter 0 register holds the current value of prescale counter This register is shown in Figure 17 17 and described in Table 17 7 Figure 17 17 RTI Up Counter 0 Register RTIUC0 offset 1...

Page 601: ...the RTI clock If CPUC0 0 then fFRC0 RTICLK 232 1 Setting CPUC0 equal to 0 is not recommended Doing so will hold the Up Counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0 If CPUC...

Page 602: ...sures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register even if another capture event happens in between the two reads A read of this register returns the va...

Page 603: ...register holds the current value of the up counter 1 and prescales the RTI clock It will be only updated by a previous read of free running counter 1 RTIFRC1 This method of updating effectively gives...

Page 604: ...are Up Counter 1 Register RTICPUC1 Field Descriptions Bit Field Value Description 31 0 CPUC1 0 FFFF FFFFh Compare up counter 1 This register holds the compare value which is compared with the up count...

Page 605: ...ure control block A read of this register returns the value of RTIFRC1 on a capture event 17 3 14 RTI Capture Up Counter 1 Register RTICAUC1 The capture up counter 1 register holds the current value o...

Page 606: ...e a DMA request A read of this register will return the current compare value A write to this register in privileged mode only will update the compare register with a new compare value 17 3 16 RTI Upd...

Page 607: ...ble to initiate a DMA request A read of this register will return the current compare value A write to this register will update the compare register with a new compare value 17 3 18 RTI Update Compar...

Page 608: ...to initiate a DMA request A read of this register will return the current compare value A write to this register in privileged mode only will provide a new compare value 17 3 20 RTI Update Compare 2...

Page 609: ...is possible to initiate a DMA request A read of this register will return the current compare value A write to this register will provide a new compare value 17 3 22 RTI Update Compare 3 Register RTI...

Page 610: ...value is updated If TBEXT 1 The compare value is not changed 17 3 24 RTI Timebase High Compare Register RTITBHCOMP The timebase high compare register holds the value to deactivate the edge detection...

Page 611: ...Control Register RTISETINTENA Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads return 0 Writes have no effect 18 SETOVL1INT Set free running counter 1 overflow interrupt 0 Read I...

Page 612: ...enabled 7 4 Reserved 0 Reads return 0 Writes have no effect 3 SETINT3 Set compare interrupt 3 0 Read Interrupt is disabled Write Corresponding bit is unchanged 1 Read or Write Interrupt is enabled 2...

Page 613: ...TI Clear Interrupt Control Register RTICLEARINTENA Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads return 0 Writes have no effect 18 CLEAROVL1INT Clear free running counter 1 ove...

Page 614: ...nged 1 Read DMA request is enabled Write DMA request is disabled 7 4 Reserved 0 Reads return 0 Writes have no effect 3 CLEARINT3 Clear compare interrupt 3 0 Read Interrupt is disabled Write Correspond...

Page 615: ...Interrupt is pending Write Bit is cleared to 0 17 OVL0INT Free running counter 0 overflow interrupt flag This bit determines if an interrupt is pending 0 Read No interrupt is pending Write Bit is unc...

Page 616: ...s disabling the watchdog This register is shown in Figure 17 38 and described in Table 17 28 Figure 17 39 Digital Watchdog Control Register RTIDWDCTRL offset 90h 31 16 DWDCTRL R WP 5312h 15 0 DWDCTRL...

Page 617: ...R W Read Write R Read only WP Write in privileged mode only n value after reset Table 17 30 Digital Watchdog Preload Register RTIDWDPRLD Field Descriptions Bit Field Value Description 31 12 Reserved...

Page 618: ...e CPU in this case Write Bit is cleared to 0 This will also clear all other status flags in the RTIWDSTATUS register Clearing of the status flags will deassert the non maskable interrupt generated due...

Page 619: ...31 16 Reserved 0 Reads return 0 and writes have no effect 15 0 WDKEY 0 FFFFh Watchdog key These bits provide the key sequence location Reads returns the current WDKEY value A write of E51Ah followed b...

Page 620: ...R 0 15 4 3 0 Reserved WWDRXN R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 17 35 Digital Windowed Watchdog Reaction Control RTIWWDRXNCTRL Fie...

Page 621: ...reset Table 17 36 Digital Windowed Watchdog Window Size Control RTIWWDSIZECTRL Field Descriptions Bit Field Value Description 31 0 WWDSIZE 0 The DWWD window size 0000 0005h 100 The functionality is th...

Page 622: ...auto clear functionality on the compare 3 interrupt 5h Read Auto clear for compare 3 interrupt is disabled Privileged Write Auto clear for compare 3 interrupt becomes disabled All other values Read Au...

Page 623: ...e in the RTIUDCP0 register Section 17 3 16 is added to this register Reads return the current compare clear value A privileged write to this register updates the compare clear value 17 3 37 RTI Compar...

Page 624: ...e in the RTIUDCP2 register Section 17 3 20 is added to this register Reads return the current compare clear value A privileged write to this register updates the compare clear value 17 3 39 RTI Compar...

Page 625: ...he cyclic redundancy check CRC controller module NOTE This chapter describes a superset implementation of the CRC module that includes features and functionality that require DMA Since not all devices...

Page 626: ...ification on any memory sub system Data compression on 8 16 32 and 64 bit data size Maximum length PSA Parallel Signature Analysis register constructed based on 64 bit primitive polynomial Each channe...

Page 627: ...Module 64 PSA Sector Signature Register 20 Bit Pattern Count Preload 20 Bit Pattern Counter CRC Status Bit 24 Bit Timeout Preload Register 24 Bit Time Out Counter 16 Bit Sector Count Preload 16 Bit Se...

Page 628: ...ch sector Signature verification can be performed automatically by CRC controller in AUTO mode or by CPU itself in Semi CPU or Full CPU mode In AUTO mode a self sustained CRC signature calculation can...

Page 629: ...inner loop is to calculate the next value of each shift register bit after one cycle 2 The outer loop is to simulate 64 cycles of shifting The equation for each shift register bit is thus built befor...

Page 630: ...sed value is always expressed in 64 bit There is a software reset per channel for PSA Signature Register When set the PSA Signature Register is reset to all zeros PSA Signature Register is reset to ze...

Page 631: ...med If the flag is not set then it means the CRC Value Register contains stale information A CRC underrun interrupt is generated When an underrun condition is detected signature verification is not pe...

Page 632: ...count register inside DMA module The DMA transfer count register is divided into two parts They are element count and frame count Note that an HW DMA request can be programmed to trigger either one f...

Page 633: ...tive Inactive Inactive 18 2 8 Pattern Count Register There is a 20 bit data pattern counter for every CRC channel The data pattern counter is a down counter and can be pre loaded with a programmable v...

Page 634: ...d in Full CPU mode Compression complete interrupt CRC fail interrupt Overrun interrupt Underrun interrupt Timeout interrupt Table 18 2 Modes in Which Interrupt Condition Can Occur AUTO Semi CPU Full C...

Page 635: ...prescaler clock which is permanently running at division 64 of HCLK clock First pattern of data must be transferred by the DMA before the timeout counter expires Watchdog timeout pre load register CRC...

Page 636: ...efore it can service the timer request Timer Time scale HW DMA req every 10 ms Data 10 9 8 7 6 5 4 3 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6 0 ms 10 ms 20 ms 30 ms 6 ms 16 ms 26...

Page 637: ...wing steps in the ISR 1 Write to software reset bit in CRC_CTRL register to reset the respective PSA Signature Register 2 Reset the CHx_MODE bits to 00 in CRC_CTRL register as Data capture mode 3 Set...

Page 638: ...Assume all DMA transfers are carried out in 64 bit transfer size 18 3 1 1 DMA Setup Set up DMA channel 1 with the starting address from which the pre determined CRC values are stored Set up the destin...

Page 639: ...1 CRC Value Register to DMA channel 1 and channel 1 PSA Signature Register to DMA channel 2 Assume all transfers carried out by DMA are in 64 bit transfer size 18 3 2 1 DMA Setup Set up DMA channel 1...

Page 640: ...to generate DMA request associated with DMA channel 1 For example an OS can set up the timer to generate a DMA request every 10ms 18 3 3 3 CRC Setup Program the pattern count to 128 Program the secto...

Page 641: ...Sector Counter Preload Register Section 18 4 10 48h CRC_CURSEC_REG1 CRC Channel 1 Current Sector Register Section 18 4 11 4Ch CRC_WDTOPLD1 CRC Channel 1 Watchdog Timeout Preload Register Section 18 4...

Page 642: ...efore CPU is required to clear this bit by writing a 0 0 PSA Signature Register is not reset 1 PSA Signature Register is reset 7 1 Reserved 0 Reads return 0 Writes have no effect 0 CH1_PSA_SWREST Chan...

Page 643: ...Writes have no effect 9 8 CH2_MODE Channel 2 Mode Selection 0 Data Capture mode In this mode the PSA Signature Register does not compress data when it is written Any data written to PSA Signature Reg...

Page 644: ...t Field Value Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 CH2_TIMEOUTENS Channel 2 Timeout Interrupt Enable Bit User and Privileged mode read 0 Timeout Interrupt is disabled 1...

Page 645: ...de write 0 No effect 1 Timeout Interrupt is enabled 3 CH1_UNDERENS Channel 1 Underrun Interrupt Enable Bit User and Privileged mode read 0 Underrun Interrupt is disabled 1 Underrun Interrupt is enable...

Page 646: ...alue Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 CH2_TIMEOUTENR Channel 2 Timeout Interrupt Enable Reset Bit User and Privileged mode read 0 Timeout Interrupt is disabled 1 Ti...

Page 647: ...e 0 No effect 1 Timeout Interrupt is disabled 3 CH1_UNDERENR Channel 1 Underrun Interrupt Enable Reset Bit User and Privileged mode read 0 Underrun Interrupt is disabled 1 Underrun Interrupt is enable...

Page 648: ...tes have no effect 12 CH2_TIMEOUT Channel 2 CRC Timeout Interrupt Status Flag This bit is set in both AUTO and Semi CPU mode User and Privileged mode read 0 No timeout interrupt is active 1 Timeout in...

Page 649: ...active 1 Timeout interrupt is active Privileged mode write 0 No effect 1 Bit is cleared 3 CH1_UNDER Channel 1 Underrun Interrupt Status Flag User and Privileged mode read 0 No Underrun Interrupt is a...

Page 650: ...errupt Offset CRC_INT_OFFSET_REG Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 OFSTREG CRC Interrupt Offset This register indicates the highes...

Page 651: ...attern of the block is compressed 7 1 Reserved 0 Reads return 0 Writes have no effect 0 CH1_BUSY CH1_BUSY During AUTO or Semi CPU mode the busy flag is set when the first data pattern of the block is...

Page 652: ...31 16 Reserved R 0 15 0 CRC_CURSEC1 R 0 LEGEND R Read only n value after reset Table 18 15 CRC Current Sector Register 1 CRC_CURSEC_REG1 Field Descriptions Bit Field Value Description 31 16 Reserved...

Page 653: ...ntains the number of clock cycles within which the DMA must transfer the next block of data patterns In Semi CPU mode this register is used to indicate the sector number for which the compression comp...

Page 654: ...1 PSA Signature High Register PSA_SIGREGH1 Figure 18 23 Channel 1 PSA Signature High Register PSA_SIGREGH1 offset 64h 31 0 PSASIG1 R W 0 LEGEND R W Read Write n value after reset Table 18 19 Channel 1...

Page 655: ...IGREGL1 Figure 18 26 Channel 1 PSA Sector Signature Low Register PSA_SECSIGREGL1 offset 70h 31 0 PSASECSIG1 R 0 LEGEND R Read only n value after reset Table 18 22 Channel 1 PSA Sector Signature Low Re...

Page 656: ...ffset 7Ch 31 0 RAW_DATA1 R 0 LEGEND R Read only n value after reset Table 18 25 Channel 1 Raw Data High Register RAW_DATAREGH1 Field Descriptions Bit Field Description 31 0 RAW_DATA1 Channel 1 Raw Dat...

Page 657: ...16 Reserved R 0 15 0 CRC_CURSEC2 R 0 LEGEND R Read only n value after reset Table 18 28 CRC Current Sector Register 2 CRC_CURSEC_REG2 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Re...

Page 658: ...ntains the number of clock cycles within which the DMA must transfer the next block of data patterns In Semi CPU mode this register is used to indicate the sector number for which the compression comp...

Page 659: ...2 PSA Signature High Register PSA_SIGREGH2 Figure 18 36 Channel 2 PSA Signature High Register PSA_SIGREGH2 offset A4h 31 0 PSASIG2 R W 0 LEGEND R W Read Write n value after reset Table 18 32 Channel 2...

Page 660: ...SIGREGL2 Figure 18 39 Channel 2 PSA Sector Signature Low Register PSA_SECSIGREGL2 offset B0h 31 0 PSASECSIG2 R 0 LEGEND R Read only n value after reset Table 18 35 Channel 2 PSA Sector Signature Low R...

Page 661: ...Raw Data Low Register RAW_DATAREGL2 Field Descriptions Bit Field Description 31 0 RAW_DATA2 Channel 2 Raw Data Low Register This register contains bits 31 0 of the uncompressed raw data 18 4 34 Chann...

Page 662: ...Module This chapter describes the behavior of the vectored interrupt manager VIM module of the device family Topic Page 19 1 Overview 663 19 2 Dual VIM for Safety 664 19 3 Device Level Interrupt Mana...

Page 663: ...CPU switches execution from the normal program flow to an interrupt service routine ISR The VIM module has the following features Dual VIM for safety Supports 127 interrupt channels in both register v...

Page 664: ...ayed by two cycles to the second instance A separate set of 2 cycle delayed versions of output ports for the CPU interrupt interface of the VIM1 are provided These will be used as one of the compare i...

Page 665: ...he address of the highest interrupt service routine ISR to the CPU Finally CPU starts executing the ISR instructions from that address in the ISR Section 19 3 1 through Section 19 3 3 provide addition...

Page 666: ...able FIQ are not reentrant After reset power reset or warm reset both FIQ and IRQ are disabled The CPU may enable these interrupt request channels individually within the CPSR Current Program Status R...

Page 667: ...After the interrupt is received by the CPU the CPU executes the instruction placed at 0x18 or 0x1C IRQ or FIQ vector to load the address of ISR interrupt vector from the interrupt vector register Exam...

Page 668: ...Q VECTOR IRQ VECTOR FIQVECREG IRQVECREG PROGRAMMABLE INTERRUPT VECTOR TABLE Phantom Vector Channel 0 Vector Channel 1 Vector Channel 126 Vector FIQINDEX IRQINDEX TO CPU VIC Port Register Register T o...

Page 669: ...errupt request With this scheme the same request can be mapped to multiple channels A lower numbered channel in each FIQ and IRQ has higher priority The programmability of the VIM allows software to c...

Page 670: ...eral Peripheral 0 Channel 0 Vector 0xFFF82004 INT_REQ1 CHAN1 Peripheral 1 Channel 1 Vector 0xFFF82008 INT_REQ2 CHAN2 Peripheral 2 Channel 2 Vector 0xFFF8200C INT_REQ3 CHAN3 Peripheral 3 Channel 3 Vect...

Page 671: ...SM Error Signal Module high level interrupt and CHAN1 is reserved for other NMI For safety reasons these two channels are mapped to FIQ only and can NOT be disabled through ENABLE registers NOTE NMI C...

Page 672: ...becomes active 19 5 Interrupt Vector Table VIM RAM Interrupt vector table stores the address of ISRs During register vectored interrupt and hardware vectored interrupt VIM accesses the interrupt vect...

Page 673: ...single bit error will be registered into SBERR flag in ECCSTAT register and the corresponding address will be captured as SBERRADDR register If SBE_INT_EN field on ECCCTL register is set to enable val...

Page 674: ...ECC checking mechanism the ECC bits allows manual insertion of faults This option is implemented using the TEST_DIAG_EN bit in the ECCCTL register control bit Once TEST_DIAG_EN is enabled the ECC bit...

Page 675: ...R and SBERRADDR registers and check for the correct address capture as well The following sequence should be used for injecting faults to data bits and testing the ECC check feature 1 Write the data l...

Page 676: ...e 19 6 VIM Wakeup Interrupt The wakeup interrupts are used to come out of low power mode LPM Any interrupt requests can be used to wake up the device After reset all interrupt requests are set to wake...

Page 677: ...wing sections provide examples about the operation of the VIM 19 8 1 Examples Configure CPU To Receive Interrupts Example 19 1 shows how to set the vector enable VE bit in the CP15 R1 register to enab...

Page 678: ...d be LDR PC PC 0x1B0 The pending ISR address is written into the corresponding vector register IRQVECREG for IRQ FIQVECREG for FIQ The CPU reads the content of the register and branches to the ISR Exa...

Page 679: ...TERRUPT PROCESSING AREA 0000001Ch ldrb R8 PC 0x21d FIQ INTERRUPT ENTRY R8 used to get the FIQ index with address pointer to the first FIQ banked register 00000020h ldr PC PC R8 LSL 2 Branch to the ind...

Page 680: ...ter 3 Section 19 9 9 20h INTREQ0 Pending Interrupt Read Location Register 0 Section 19 9 10 24h INTREQ1 Pending Interrupt Read Location Register 1 Section 19 9 10 28h INTREQ2 Pending Interrupt Read Lo...

Page 681: ...effect 8 SBERR The SBERR indicates that a single bit error has been detected and has been corrected by the SECDED logic and the Interrupt Vector Table is being used for normal operation not bypassed 0...

Page 682: ...23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 EDAC_MODE These bits determine whether Single Bit Errors SBE detected by the SECDED block will be corrected or not 5h Disable correction of...

Page 683: ...ble bit error since the flag has been clear Subsequent ECC errors will not update this register until the UERR flag has been cleared Note This register is valid only when PARFLG is set see Section 19...

Page 684: ...his register until the SBERR flag has been cleared This register provides the Interrupt Vector Table address offset from base address word aligned of the ECC error location This register is valid only...

Page 685: ...bits represent the index of the IRQ pending interrupt with the highest precedence as shown in Table 19 11 When no interrupts are pending the least significant byte of IRQINDEX is 0 19 9 8 FIQ Index O...

Page 686: ...Figure 19 20 FIQ IRQ Program Control Register 1 FIRQPR1 offset F14h 31 0 FIRQPR1 63 32 R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 19 21 FIQ IRQ Program Con...

Page 687: ...2 INTREQ2 offset 28h 31 0 INTREQ2 95 64 R W1CP 0 LEGEND R W Read Write W1CP Write 1 to clear in privilege mode only n value after reset Figure 19 26 Pending Interrupt Read Location Register 3 INTREQ3...

Page 688: ...e Set Register 1 REQENASET1 offset 34h 31 0 REQENASET1 63 32 R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 19 29 Interrupt Enable Set Register 2 REQENASET2 of...

Page 689: ...ENACLR1 offset 44h 31 0 REQENACLR1 63 32 R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 19 33 Interrupt Enable Clear Register 2 REQENACLR2 offset 48h 31 0 REQE...

Page 690: ...ENASET1 63 32 R WP FFFF FFFFh LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 19 37 Wake Up Enable Set Register 2 WAKEENASET2 offset 58h 31 0 WAKEENASET2 95 64 R WP FF...

Page 691: ...FF FFFFh LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 19 41 Wake Up Enable Clear Register 2 WAKEENACLR2 offset 68h 31 0 WAKEENACLR2 95 64 R WP FFFF FFFFh LEGEND R W...

Page 692: ...REG From Section 19 5 IRQ interrupt vector register This vector gives the address of the ISR with the highest pending IRQ request The CPU reads the address and branches to this location 19 9 16 FIQ In...

Page 693: ...alue after reset Table 19 22 Capture Event Register CAPEVT Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reads are indeterminate and writes have no effect 22 16 CAPEVTSRC1 Capture ev...

Page 694: ...INT_REQ0 and INT_REQ1 Do NOT write any value other than 0x7F to CHANMAP127 Channel 127 is reserved because no interrupt vector table entry supports this channel Figure 19 46 Interrupt Control Registe...

Page 695: ...hannel CHANx2 maps to 0 Read Interrupt request 0 maps to channel priority CHANx2 Write The default value of this bit after reset is given in Table 19 23 The channel priority CHANx2 is set with the int...

Page 696: ...rporated Direct Memory Access Controller DMA Module Chapter 20 SPNU563A March 2018 Direct Memory Access Controller DMA Module This chapter describes the direct memory access DMA controller Topic Page...

Page 697: ...rotected by ECC Multiple logical channels with individual enable refer to the data manual for the number of channels on your device Channel chaining capability 48 peripheral DMA requests Hardware and...

Page 698: ...rbiter Control Regs Control Packet RAM Interrupt Manager Port A Port B BTC FTC BER LFS HBC MPV interrupts CPU I F Errors Single Double Bit Errors Hardware Events Overview www ti com 698 SPNU563A March...

Page 699: ...the respective channels in the PARx registers 20 2 Module Operation The DMA acts as an independent master in the platform architecture DMA will attempt to execute up to two channels at the same time...

Page 700: ...nation in the control packet Control packets store the transfer information such as source address destination address transfer count and control attributes for each channel 20 2 2 DMA Data Access The...

Page 701: ...l packet contains channel information such as source address destination address transfer count element frame offset value and channel configuration Source address destination address and transfer cou...

Page 702: ...0x810 0x8F0 Base 0xXXXC Reserved 0x10 Primary CP0 Primary CP1 Primary CPnn Working CP0 Working CP1 Working CPnn Base 0XXX0 Base 0xXXX4 Base 0xXXX8 Initial Source Address Channel Configuration Initial...

Page 703: ...uration defines the following individual parameters Read element size Write element size Trigger type frame or block Addressing mode for source Addressing mode for destination Auto initiation mode Nex...

Page 704: ...following setup Read Element Size 8 bit Write Element Size 8 bit Element Count 2 Frame Count 4 f2 f3 f4 f1 Module Operation www ti com 704 SPNU563A March 2018 Submit Documentation Feedback Copyright 2...

Page 705: ...r DMA Module Figure 20 8 DMA Indexing Example 2 20 2 5 Priority Queue User can assign channels in to priority queues to facilitate request handling during arbitration The port has two priority queues...

Page 706: ...ueue then the DMA switches to service low queue channels Rotating Channels are arbitrated by using the round robin scheme Arbitration is performed when the FIFO is empty When there are no pending chan...

Page 707: ...shows an example of data unpacking in which the DMA is used to transfer 128 transmit data elements to the MibSPI FIFO buffer In this example data unpacking is required because the read element size is...

Page 708: ...npacking When the read element size is smaller than the write element size the DMA controller needs to perform data packing The number of elements to pack is equal to the ratio between the write eleme...

Page 709: ...le Operation 709 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Direct Memory Access Controller DMA Module Figure 20 13 Example of DMA Data Packing For...

Page 710: ...time Additional requests are ignored until at least one pending request is completely processed The DMA controller also supports a mix of hardware and software requests on the same channel Note that s...

Page 711: ...DMAREQ 0 MIBSPI1 12 MIBSPI3 12 DMAREQ 26 CRC1 MIBSPI1 MIBSPI3 CRC1 DMAREQ 1 MIBSPI1 13 MIBSPI3 13 DMAREQ 27 LIN1 MIBSPI5 LIN1 receive MIBSPI5 14 DMAREQ 28 LIN1 MIBSPI5 LIN1 transmit MIBSPI5 15 DMAREQ...

Page 712: ...t can be issued when a bus error Illegal transaction with ok response is detected The imprecise read error is connected to the ESM module External imprecise error on write an interrupt can be issued w...

Page 713: ...O U P A DMA S C R DMA DMM imprecise read error Group 1 5 DMA DMM imprecise write error Group 1 13 www ti com Module Operation 713 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas...

Page 714: ...de was entered will finish its entire frame or block transfer after suspend mode ends depending how the debug option was chosen To facilitate debugging a Watch Point Register Section 20 3 1 54 and a W...

Page 715: ...switching latency in between channels When bypass mode is enabled the DMA performs minimal transfers within an arbitration boundary In addition the bypass feature allows arbitration between channels t...

Page 716: ...4 needs to be enabled for all chained channels before triggering first DMA request Figure 20 16 illustrates how internally chained request is generated after completing the required transfers and sto...

Page 717: ...appropriate accesses The access privileges can be set to one of four permission settings as shown below Full access Read only access Write only access No access The permissions for a given region are...

Page 718: ...gister is 0xA the error is automatically corrected The SBEFLG bit in the register is also set to 1 to indicate a single bit error was corrected The DMAECCSBE register is updated to indicate the error...

Page 719: ...DMAPAR similarly for single bit error read SBERR in DMASECCCTRL and error address in DMAECCSBE 7 The check is successful if the flag and error address are updated successfully 8 Clear the flags EDFLG...

Page 720: ...SET register Also the error is indicated to the ESM module This is shown in Figure 20 18 Since the channel stops due to an error and likely the peripheral and the DMA are out of synchronization it is...

Page 721: ...Register Section 20 3 1 10 44h GCHIENAS Global Channel Interrupt Enable Set Register Section 20 3 1 11 4Ch GCHIENAR Global Channel Interrupt Enable Reset Register Section 20 3 1 12 54h DREQASI0 DMA Re...

Page 722: ...ter Section 20 3 1 57 1A0h FBACTC FIFO B Active Channel Transfer Address Register Section 20 3 1 58 1A8h DMAPECR Parity Control Register Section 20 3 1 62 1ACh DMAPAR DMA Parity Error Address Register...

Page 723: ...Event Control Register Section 20 3 1 90 344h TERFLAG TER Event Flag Register Section 20 3 1 91 348h TERROFFSET TER Event Channel Offset Register Section 20 3 1 92 Table 20 8 Control Packet Memory Map...

Page 724: ...to prevent state machines from carrying out bus transactions If DMA_EN bit is cleared in the middle of an bus transaction the state machine will stop at an arbitration boundary 0 The DMA is disabled...

Page 725: ...nd of a frame or a block transfer depending on how the channel is triggered as programmed in the TTYPE bit field of CHCTRL The control packet is modified after the pending bit is set A bus error occur...

Page 726: ...1 30 29 28 27 16 SCHEME Reserved FUNC R 1 R 0 R A0Dh 15 11 10 8 7 6 5 0 Reserved MAJOR Reserved MINOR R 0 R 0 R 0 R 3h LEGEND R Read only n value after reset Table 20 12 DMA Revision ID Register Descr...

Page 727: ...matically for the following conditions At the end of a block transfer if the auto initiation bit AIM see CHCTRL is not active If a bus error is detected for an active channel Reading from HWCHENAS giv...

Page 728: ...it is set The corresponding bit is cleared after one block transfer when TTYPE bit is programmed for blocks transfer and if the corresponding bit in HW channel enable register HWCHENAS is enabled When...

Page 729: ...ead The corresponding channel is assigned to the low priority queue Write No effect 1 Read and write The corresponding channel is assigned to high priority queue 20 3 1 10 Channel Priority Reset Regis...

Page 730: ...ds to channel 1 and so on 0 Read The corresponding channel is disabled for interrupt Write No effect 1 Read and write The corresponding channel is enabled for interrupt 20 3 1 12 Global Channel Interr...

Page 731: ...0 assignment This bit field chooses the DMA request assignment for channel 0 0 DMA request line 0 triggers channel 0 2Fh DMA request line 47 triggers channel 0 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 732: ...4 assignment This bit field chooses the DMA request assignment for channel 4 0 DMA request line 0 triggers channel 4 2Fh DMA request line 47 triggers channel 4 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 733: ...ssignment This bit field chooses the DMA request assignment for channel 8 0 DMA request line 0 triggers channel 8 2Fh DMA request line 47 triggers channel 8 30h 3Fh Reserved 23 22 Reserved 0 Reads ret...

Page 734: ...ignment This bit field chooses the DMA request assignment for channel 12 0 DMA request line 0 triggers channel 12 2Fh DMA request line 47 triggers channel 12 30h 3Fh Reserved 23 22 Reserved 0 Reads re...

Page 735: ...ssignment This bit field chooses the DMA request assignment for channel 16 0 DMA request line 0 triggers channel 16 2Fh DMA request line 47 triggers channel 16 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 736: ...ssignment This bit field chooses the DMA request assignment for channel 20 0 DMA request line 0 triggers channel 20 2Fh DMA request line 47 triggers channel 20 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 737: ...ssignment This bit field chooses the DMA request assignment for channel 24 0 DMA request line 0 triggers channel 24 2Fh DMA request line 47 triggers channel 24 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 738: ...ssignment This bit field chooses the DMA request assignment for channel 28 0 DMA request line 0 triggers channel 28 2Fh DMA request line 47 triggers channel 28 30h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 739: ...0 Writes have no effect 26 24 CH1PA 0 7h These bit fields determine to which port channel 1 is assigned Refer to CH0PA for bit value descriptions 23 Reserved 0 Reads return 0 Writes have no effect 22...

Page 740: ...ites have no effect 26 24 CH9PA 0 7h These bit fields determine to which port channel 9 is assigned Refer to CH8PA for bit value descriptions 23 Reserved 0 Reads return 0 Writes have no effect 22 20 C...

Page 741: ...have no effect 26 24 CH17PA 0 7h These bit fields determine to which port channel 17 is assigned Refer to CH16PA for bit value descriptions 23 Reserved 0 Reads return 0 Writes have no effect 22 20 CH1...

Page 742: ...es have no effect 26 24 CH25PA 0 7h These bit fields determine to which port channel 25 is assigned Refer to CH24PA for bit value descriptions 23 Reserved 0 Reads return 0 Writes have no effect 22 20...

Page 743: ...r LFSMAP offset BCh 31 0 LFSAB 31 0 R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 20 34 LFS Interrupt Mapping Register LFSMAP Field Descriptions Bit Field Valu...

Page 744: ...CMAP offset CCh 31 0 BTCAB 31 0 R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 20 36 BTC Interrupt Mapping Register BTCMAP Field Descriptions Bit Field Value De...

Page 745: ...1 corresponds to channel 1 and so on 0 Read Corresponding FTC interrupt of a channel is disabled Write No effect 1 Read and write FTC interrupt of the corresponding channel is enabled 20 3 1 30 FTC I...

Page 746: ...hannel 1 and so on 0 Read Corresponding LFS interrupt of a channel is disabled Write No effect 1 Read and write LFS interrupt of the corresponding channel is disabled 20 3 1 32 LFS Interrupt Enable Re...

Page 747: ...annel 1 and so on 0 Read HBC interrupt of the corresponding channel is disabled Write No effect 1 Read and write HBC interrupt of the corresponding channel is enabled 20 3 1 34 HBC Interrupt Enable Re...

Page 748: ...hannel 1 and so on 0 Read BTC interrupt of the corresponding channel is disabled Write No effect 1 Read and write BTC interrupt of the corresponding channel is enabled 20 3 1 36 BTC Interrupt Enable R...

Page 749: ...el 1 One or more of the interrupt types FTC LFS HBC or BTC is pending on the corresponding channel 20 3 1 38 FTC Interrupt Flag Register FTCFLAG Figure 20 56 FTC Interrupt Flag Register FTCFLAG offset...

Page 750: ...t enable bit is cleared 0 Read LFS interrupt of the corresponding channel is not pending Write No effect 1 Read LFS interrupt of the corresponding channel is pending Write The flag is cleared 20 3 1 4...

Page 751: ...t 1 corresponds to channel 1 and so on Note Reading from the respective interrupt channel offset register also clears the corresponding flag see Section 20 3 1 46 and Section 20 3 1 50 Note The state...

Page 752: ...TCA Interrupt Channel Offset Register FTCAOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 753: ...FSA Interrupt Channel Offset Register LFSAOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 754: ...BCA Interrupt Channel Offset Register HBCAOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 755: ...TCA Interrupt Channel Offset Register BTCAOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 756: ...TCB Interrupt Channel Offset Register FTCBOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 757: ...FSB Interrupt Channel Offset Register LFSBOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 758: ...BCB Interrupt Channel Offset Register HBCBOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 759: ...TCB Interrupt Channel Offset Register BTCBOFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed a...

Page 760: ...to this bit limits the FIFO depth to the size of one element That means that after one element is read the write out to the destination will begin This feature is particularly useful to minimize swit...

Page 761: ...served RTC R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in privilege mode only n value after reset Table 20 59 RAM Test Control Register RTCTRL Field Descriptions Bit Field Value Description...

Page 762: ...field indicates the channel number that causes the watch point to match 23 17 Reserved 0 Reads return 0 Writes have no effect 16 DMADBGS DMA debug status When a watch point is set up to watch for a u...

Page 763: ...with the watch mask register WMR When the DBGEN bit in the DCTRL register is set and a unique address or a range of addresses are detected on the AHB address bus of Port B a debug request signal is s...

Page 764: ...Active Channel Destination Address Register FAACDADDR Field Descriptions Bit Field Description 31 0 FAACDA FIFO A Active Channel Destination Address This register contains the current destination addr...

Page 765: ...Active Channel Destination Address Register FBACDADDR Field Descriptions Bit Field Description 31 0 FBACDA FIFO B Active Channel Destination Address This register contains the current destination addr...

Page 766: ...isabled immediately If a frame on control packet x is processed at the time the parity error is detected then remaining elements of this frame will not be transferred anymore The DMA will be disabled...

Page 767: ...ptions Bit Field Value Description 31 25 Reserved 0 Reads return 0 Writes have no effect 24 EDFLAG ECC Error Detection Flag This flag indicates if an ECC error occurred on reading DMA Control packet R...

Page 768: ...upt is routed to the VIM Group A 1 The interrupt is routed to the second CPU Group B 27 INT3ENA Interrupt enable of region 3 0 The interrupt is disabled 1 The interrupt is enabled 26 25 REG3AP Region...

Page 769: ...es are allowed 1h Read only accesses are allowed 2h Write only accesses are allowed 3h No accesses are allowed 8 REG1ENA Region 1 enable 0 The region is disabled no address checking done 1 The region...

Page 770: ...ether an access permission violation was detected in this region 0 Read No fault was detected Write No effect 1 Read A fault was detected Write The bit was cleared 23 17 Reserved 0 Reads return 0 Writ...

Page 771: ...3 1 67 DMA Memory Protection Region 0 End Address Register DMAMPR0E Figure 20 84 DMA Memory Protection Region 0 End Address Register DMAMPR0E offset 1BCh 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 772: ...3 1 69 DMA Memory Protection Region 1 End Address Register DMAMPR1E Figure 20 86 DMA Memory Protection Region 1 End Address Register DMAMPR1E offset 1C4h 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 773: ...3 1 71 DMA Memory Protection Region 2 End Address Register DMAMPR2E Figure 20 88 DMA Memory Protection Region 2 End Address Register DMAMPR2E offset 1CCh 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 774: ...3 1 73 DMA Memory Protection Region 3 End Address Register DMAMPR3E Figure 20 90 DMA Memory Protection Region 3 End Address Register DMAMPR3E offset 1D4h 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 775: ...upt is routed to the VIM Group A 1 The interrupt is routed to the second CPU Group B 27 INT7ENA Interrupt enable of region 7 0 The interrupt is disabled 1 The interrupt is enabled 26 25 REG7AP Region...

Page 776: ...es are allowed 1h Read only accesses are allowed 2h Write only accesses are allowed 3h No accesses are allowed 8 REG5ENA Region 5 enable 0 The region is disabled no address checking done 1 The region...

Page 777: ...ermines whether an access permission violation was detected in this region 0 Read No fault was detected Write No effect 1 Read A fault was detected Write Clears the bit 23 17 Reserved 0 Reads return 0...

Page 778: ...3 1 77 DMA Memory Protection Region 4 End Address Register DMAMPR4E Figure 20 94 DMA Memory Protection Region 4 End Address Register DMAMPR4E offset 1E4h 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 779: ...3 1 79 DMA Memory Protection Region 5 End Address Register DMAMPR5E Figure 20 96 DMA Memory Protection Region 5 End Address Register DMAMPR5E offset 1ECh 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 780: ...3 1 81 DMA Memory Protection Region 6 End Address Register DMAMPR6E Figure 20 98 DMA Memory Protection Region 6 End Address Register DMAMPR6E offset 1F4h 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 781: ...1 83 DMA Memory Protection Region 7 End Address Register DMAMPR7E Figure 20 100 DMA Memory Protection Region 7 End Address Register DMAMPR7E offset 1FCh 31 0 ENDADDRESS R WP 0 LEGEND R W Read Write W...

Page 782: ...ege mode only n value after reset Table 20 91 DMA Single Bit ECC Control Register DMASECCCTRL Field Description Bit Field Value Description 31 17 Reserved 0 Reads return 0 Writes have no effect 16 SBE...

Page 783: ...eld Descriptions Bit Field Value Description 31 12 Reserved 0 Reads return 0 Writes have no effect 11 0 ERRORADDRESS 0 FFFh The DMA RAM address offset from base address word aligned of the ECC error l...

Page 784: ...tatus of a channel currently being processed remains active even if emulation mode is entered or DMA is disabled by way of the DMA_EN bit Up to 1 bit can be set in this register at any given time 20 3...

Page 785: ...that is request lines 63 to 32 Bit 0 corresponds to DMA Request line 32 bit 1 corresponds to DMA Request line 33 and so on 0 DMA Request polarity is active high 1 DMA Request polarity is active low 20...

Page 786: ...ransaction error has occurred Write Clears the bit 15 4 Reserved 0 Reads return 0 Writes have no effect 3 0 TER_EN Transaction error event detection enable 5h Write Disable transaction error event det...

Page 787: ...erved 0 Reads return 0 Writes have no effect 7 6 sbz 0 These bits should always be programmed as zero 5 0 TER_OFF This register provides the offset of the first channel number that encountered bus par...

Page 788: ...ontrol packets look the same Following there is the detailed layout of these registers shown for control packet 0 20 3 2 1 Initial Source Address Register ISADDR Figure 20 110 Initial Source Address R...

Page 789: ...Field Value Description 31 29 Reserved 0 Reads are undefined Writes have no effect 28 16 IFTCOUNT 0 1FFFh Initial frame transfer count These bits define the number of frame transfers 15 13 Reserved 0...

Page 790: ...lected 21h 3Fh Reserved 15 14 RES Read element size 0 The element is byte 8 bit 1h The element is half word 16 bit 2h The element is word 32 bit 3h The element is double word 64 bit 13 12 WES Write el...

Page 791: ...15 13 Reserved 0 Reads are undefined Writes have no effect 12 0 EIDXS 0 1FFFh Source address element index These bits define the offset to be added to the source address after each element transfer 2...

Page 792: ...t Table 20 107 Current Destination Address Register CDADDR Field Descriptions Bit Field Description 31 0 CDADDR Current destination address These bits contain the current working absolute 32 bit desti...

Page 793: ...Incorporated External Memory Interface EMIF Chapter 21 SPNU563A March 2018 External Memory Interface EMIF This chapter describes the external memory Interface EMIF Topic Page 21 1 Introduction 794 21...

Page 794: ...synchronous memories to extend the memory access The EMIF module supports up to 3 chip selects EMIF_nCS 4 2 Each chip select has the following individually programmable attributes Data Bus Width Read...

Page 795: ...pyright 2018 Texas Instruments Incorporated External Memory Interface EMIF 21 1 3 Functional Block Diagram Figure 21 1 illustrates the connections between the EMIF and its internal requesters along wi...

Page 796: ...rocessed In some cases the EMIF will perform one or more auto refresh cycles before processing the request For details on the EMIF s internal arbitration between performing requests and performing aut...

Page 797: ...mmands to the device EMIF_CKE O Clock enable pin This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the SELF REFRESH command which places the device in self refr...

Page 798: ...t access READ Read The READ command outputs the starting column address and signals the SDRAM to begin the burst read operation Address EMIF_A 10 is always pulled low to avoid auto precharge This allo...

Page 799: ...Waveform of SDRAM PRE Command 21 2 5 2 Interfacing to SDRAM The EMIF supports a glueless interface to SDRAM devices with the following characteristics Pre charge bit is A 10 The number of column addr...

Page 800: ...Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface EMIF Figure 21 4 EMIF to 512K 16 2 bank SDRAM Interface Table 21 6 16 bit EMIF Address Pin Connections S...

Page 801: ...ntering power down mode NM Narrow Mode This bit defines the width of the data bus between the EMIF and the attached SDRAM device When set to 1 the data bus is set to 16 bits When set to 0 the data bus...

Page 802: ...RAM and Asynchronous interfaces are performed until this auto initialization is complete A write is performed to any of the three least significant bytes of the SDRAM configuration register SDCR An SD...

Page 803: ...d 1 Place the SDRAM into Self Refresh Mode by setting the SR bit of SDCR to 1 A byte write to the upper byte of SDCR should be used to avoid restarting the SDRAM Auto Initialization Sequence described...

Page 804: ...the RR field of SDRCR The two counters used to perform auto refresh cycles are a 13 bit refresh interval counter and a 4 bit refresh backlog counter At reset and upon writing to the RR field the refr...

Page 805: ...state by setting the SR bit of SDCR to 1 This will cause the EMIF to issue the SLFR command after completing any outstanding SDRAM access requests and clearing the refresh backlog counter by performin...

Page 806: ...e SDRAM are closed precharged prior to issuing the POWER DOWN command Therefore the EMIF only supports Precharge Power Down The EMIF does not support Active Power Down where internal banks of the SDRA...

Page 807: ...onfigured to 16 bit by setting the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 21 5 shows a burst size of eight The EMIF will truncate a series of burstin...

Page 808: ...e NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 21 6 shows a burst size of eight Figure 21 6 Timing Waveform for Basic SDRAM Write Operation The EMIF will t...

Page 809: ...his method of traversal through the SDRAM banks helps maximize the number of open banks inside of the SDRAM and results in an efficient use of the device There is no limitation on the number of banks...

Page 810: ...ces The second mode of operation is Select Strobe Mode in which the EMIF_nCS 4 2 pins act as a strobe active only during the strobe period of an access In this mode the EMIF_nDQM pins of the EMIF func...

Page 811: ...8 bit asynchronous device the EMIF_BA 1 and EMIF_BA 0 pins provide the least significant bits of the halfword or byte address respectively Additionally when the EMIF interfaces to a 16 bit asynchrono...

Page 812: ...details on this mode of operation W_SETUP R_SETUP Read Write setup widths These fields define the number of EMIF clock cycles of setup time for the address pins EMIF_A and EMIF_BA byte enables EMIF_n...

Page 813: ...od MAX_EXT_WAIT Maximum Extended Wait Cycles This field configures the number of EMIF clock cycles the EMIF will wait for the EMIF_nWAIT pin to be deactivated during the strobe period of an access cyc...

Page 814: ...n was directly proceeded by a write operation and the TA field has been cleared to 0 one turn around cycle will be inserted After the EMIF has waited for the turnaround cycles to complete it again che...

Page 815: ...be Hold 2 3 2 Address Data Byte enable www ti com EMIF Module Architecture 815 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface...

Page 816: ...ill its highest priority task If so the EMIF proceeds to the setup period of the operation If it is no longer the highest priority task the EMIF terminates the operation Start of the setup period The...

Page 817: ...old 2 3 2 Address Data Address Byte enable www ti com EMIF Module Architecture 817 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Inter...

Page 818: ...nother read operation no turn around cycles are inserted If the current read operation was directly proceeded by a write operation and the TA field has been cleared to 0 one turn around cycle will be...

Page 819: ...old 2 3 2 Byte enables Address Data www ti com EMIF Module Architecture 819 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface EM...

Page 820: ...urnaround cycles to complete it again checks to make sure that the write operation is still its highest priority task If so the EMIF proceeds to the setup period of the operation If it is no longer th...

Page 821: ...to the device data manual for details on the timing requirements of the EMIF_nWAIT signal The EMIF_nWAIT pin cannot be used to extend the strobe period indefinitely The programmable MAX_EXT_WAIT fiel...

Page 822: ...bled when using the asynchronous interface in Page mode Figure 21 14 Asynchronous Read in Page Mode 21 2 7 Data Bus Parking The EMIF always drives the data bus to the previous write data value when it...

Page 823: ...is not affected by the WPn bit in the asynchronous wait cycle configuration register AWCC The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert t...

Page 824: ...been enabled by writing a 1 to the AT_MASK_SET bit in INTMSKSET LT_MASKED This bit is set only when line trap interrupt occurs and the interrupt has been enabled by writing a 1 to the LT_MASK_SET bit...

Page 825: ...according to the following priority scheme highest priority listed first 1 If the EMIF s backlog refresh counter is at the Refresh Must urgency level the EMIF performs multiple SDRAM auto refresh cyc...

Page 826: ...a 16 bit data bus The maximum request size that the EMIF can be sent is 16 words therefore the maximum number of access cycles per memory request is 64 when the EMIF is configured with an 8 bit data b...

Page 827: ...es to follow when stopping the EMIF memory controller clocks 21 2 15 1 Power Management Using Self Refresh Mode The EMIF can be placed into a self refresh state in order to place the attached SDRAM de...

Page 828: ...ister Section 21 3 2 08h SDCR SDRAM Configuration Register Section 21 3 3 0Ch SDRCR SDRAM Refresh Control Register Section 21 3 4 10h CE2CFG Asynchronous 1 Configuration Register Section 21 3 5 14h CE...

Page 829: ...n is high 28 WP0 EMIF_nWAIT 0 polarity bit This bit defines the polarity of the EMIF_nWAIT 0 pin 0 Insert wait cycles if EMIF_nWAIT 0 pin is low 1 Insert wait cycles if EMIF_nWAIT 0 pin is high 27 24...

Page 830: ...ection 21 2 5 7 The field should be written using a byte write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence 0 Writing a 0 to this bit will cause connected SDRAM devi...

Page 831: ...h 7h Reserved 3 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 0 PAGESIZE Page Size This field defines the internal pa...

Page 832: ...FG Field Descriptions Bit Field Value Description 31 SS Select Strobe bit This bit defines whether the asynchronous interface operates in Normal Mode or Select Strobe Mode See Section 21 2 6 for detai...

Page 833: ...ved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 22 20 T_RCD 0 7h Specifies the Trcd value of the SDRAM This defines the minimum number of...

Page 834: ...her command The SDSRETR is shown in Figure 21 21 and described in Table 21 31 Figure 21 21 SDRAM Self Refresh Exit Timing Register SDSRETR offset 3Ch 31 16 Reserved R 0 15 5 4 0 Reserved T_XS R 0 R W...

Page 835: ...eserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 WR Wait Rise This bit is set to 1 by hardware to indicate that a rising edge on the...

Page 836: ...as 0 If writing to this field always write the default value of 0 2 WR_MASKED Wait Rise Masked This bit is set to 1 by hardware to indicate a rising edge has occurred on the EMIF_nWAIT pin provided th...

Page 837: ...ET Wait Rise Mask Set This bit determines whether or not the wait rise Interrupt is enabled Writing a 1 to this bit sets this bit sets the WR_MASK_CLR bit in the EMIF interrupt mask clear register INT...

Page 838: ...ears this bit clears the WR_MASK_SET bit in the EMIF interrupt mask set register INTMSKSET and disables the wait rise interrupt To set this bit a 1 must be written to the WR_MASK_SET bit in INTMSKSET...

Page 839: ...G_DEL 1 3Fh Page access delay for NOR Flash connected on CS4 Number of EMIF_CLK cycles required for the page read data to be valid minus one cycle This value must not be cleared to 0 17 CS4_PG_SIZE Pa...

Page 840: ...interface the EMIF with the Samsung K4S641632H TC L 70 SDRAM and the SHARP LH28F800BJE PTTL90 8Mb Flash memory 21 4 2 1 Configuring the SDRAM Interface This section describes how to configure the EMIF...

Page 841: ...CE nCAS nRAS nWE CLK CKE BA 1 BA 0 A 11 0 LDQM UDQM DQ 15 0 FLASH 512k x 16 A 0 A 12 1 DQ 15 0 nCE nWE nOE nRESET A 18 13 RY BY nBYTE0 nBYTE1 FLASH 512k x 16 A 0 A 12 1 DQ 15 0 nCE nWE nOE nRESET A 18...

Page 842: ...es tRC as the minimum auto refresh period 2 The Samsung datasheet does not specify a tWR value Instead Samsung specifies tRDL as last data in to row precharge minimum delay Table 21 38 SDTIMR Field Ca...

Page 843: ...for the EMIF to K4S641632H TC L 70 Interface Field Name Formula Value from K4S641632H TC L 70 Datasheet Value Calculated for Field T_XS T_XS tXSR fEMIF_CLK 1 tRC 68 ns min 1 6 Figure 21 29 SDRAM Self...

Page 844: ...h should be written to SDCR Figure 21 31 shows how SDCR should be programmed The EMIF is now ready to perform read and write accesses to the SDRAM Table 21 41 SDCR Field Values For the EMIF to K4S6416...

Page 845: ...to 1 to select a 16 bit interface The other fields in this register control the shaping of the EMIF signals and the proper values can be determined by referring to the AC Characteristics in the Flash...

Page 846: ...MHz 1 R_STROBE 9 35 R_STROBE 10 The R_HOLD field must be large enough to satisfy the EMIF Data hold time tH R_HOLD tH fEMIF_CLK 1 R_HOLD 1 ns 100 MHz 1 R_HOLD 0 9 The R_HOLD field must also combine w...

Page 847: ...TROBE W_HOLD tAVAV fEMIF_CLK 3 W_SETUP W_STROBE W_HOLD 90 ns 100 MHz 3 W_SETUP W_STROBE W_HOLD 6 Solving the above equations for the Write fields results in the following possible solution W_SETUP 1 W...

Page 848: ...ments Incorporated Analog To Digital Converter ADC Module Chapter 22 SPNU563A March 2018 Analog To Digital Converter ADC Module This chapter describes the analog to digital converter ADC interface mod...

Page 849: ...e divided between the three conversion groups and are configurable by software Accesses to the conversion result RAM are protected by parity Flexible options for generating DMA requests for transferri...

Page 850: ...e 16 analog input channels The connections are shown in Figure 22 1 ADC1 supports 32 channels ADC2 supports 25 channels of which 16 channels are shared with ADC1 When using both ADC1 and ADC2 on a sha...

Page 851: ..._INT GP1_INT EV_INT MAG_THR_INT 5 0 Analog Core Interface Input Channel Selection 32 SWCNTRL 3 0 Samp_Cap_Discharge Interrupt Generation GP1_DMA_REQ DMA Generation Request ADEVSRC EV_SRC 2 0 ADG1SRC G...

Page 852: ...the start of the sampling period The analog input signal is sampled directly on to the switched capacitor array during this period providing an inherent sample and hold function The sampling period en...

Page 853: ...and Group2 are software triggered by default and can be configured to be hardware or event triggered as well The triggering of conversions in each group is discussed in Section 22 2 1 6 Each conversi...

Page 854: ...ch group has its own mode control register The MODE field of these control registers allow the application to select between a single conversion sequence or continuous conversion mode NOTE Selecting c...

Page 855: ...ers with each buffer capable of holding one conversion result The number of buffers allocated for each group is programmed by configuring the ADC module registers ADBNDCR and ADBNDEND ADBNDCR contains...

Page 856: ...ult Read from FIFO 10 bit ADC Offset Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x90 to 0xAF ADEVBUFFER Reserved EV_ EMPTY EV_CHID EV_DR 0xB...

Page 857: ...7 Format of Conversion Result Directly Read from ADC RAM 12 bit ADC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC RAM address Reserved channel id 4 channel...

Page 858: ...the three memory regions as shown in Figure 22 9 Suppose that the CPU wants to read out the results for the Event Group from a FIFO queue The CPU needs to read from any address in the range ADEVBUFFE...

Page 859: ...der into the Clock Control Register ADCLOCKCR 4 Configure the acquisition time for the group that is to be used For example configure the Group1 Sampling Time Control Register ADG1SAMP to set the acqu...

Page 860: ...erved No Reset On ChnSel Reserved EV_DATA_FMT Reserved EV_ CHID OVR_ EV_ RAM_ IGN Rsvd EV_ 8BIT EV_ MODE FRZ_ EV 0x014 ADG1MODECR Reserved No Reset On ChnSel Reserved G1_DATA_FMT Reserved G1_ CHID OVR...

Page 861: ...hat channel number in the group s channel select register 22 2 2 2 2 Enhanced Channel Selection Mode There are some important concepts related to the enhanced channel selection mode These are defined...

Page 862: ...group Figure 22 11 Example Look Up Table Entry 31 16 Reserved R 0 15 13 12 8 7 5 4 0 Reserved EV_EXT_CHN_MUX_SEL Reserved EV_INT_CHN_MUX_SEL R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n va...

Page 863: ...SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Analog To Digital Converter ADC Module 22 2 2 2 2 2 Example ADC Conversion Sequence Using Enhanced Chann...

Page 864: ...that G1_CURRENT_COUNT is incremented from 0 to 1 Next Channel Selection There are two bits set in the ADG1SEL register so that the ADC module now uses the G1_CURRENT_COUNT value of 1 to index the Grou...

Page 865: ...continuous conversion mode gets serviced by the ADC continuously The group still needs to be triggered appropriately for the first conversion to start The conversions are performed continuously there...

Page 866: ...his case the ADC allows two options If the OVR_RAM_IGN bit in the group s operating mode control register ADEVMODECR ADG1MODECR ADG2MODECR is set then the ADC module ignores the contents of the group...

Page 867: ...in 10 bit Resolution The DATA_FMT field is not effective in this mode and the application has the choice to read either the full 10 bit conversion result or an 8 bit conversion result This is controll...

Page 868: ...CPU is interrupted This feature can be used to significantly reduce the CPU load when using interrupts for reading the conversion results The group s threshold register needs to be configured before t...

Page 869: ...be left cleared default if a DMA request is desired to be generated for new results getting written to the results memory 22 2 4 2 DMA Request for a Fixed Number of Conversion Results This mode is ena...

Page 870: ...ersion result can be masked off by writing 0xf to the interrupt comparison mask register allowing a gross comparison to be made By default the full 10 12 bit conversion results are compared 22 2 5 3 M...

Page 871: ...th minimum noise Calibration mode is enabled by setting the CAL_EN bit ADCALCR 0 The application needs to ensure that no conversion group is being serviced when the calibration mode is enabled The inp...

Page 872: ...libration conversion When the calibration conversion is interrupted by an ADC_Enable ADC_EN 0 CAL_EN 1 and CAL_ST 1 a new conversion is automatically restarted as soon as the ADC_Enable bit is release...

Page 873: ...cess deviation Consequently the mid point voltage s accuracy can be affected due to the imperfections in the two resistors expected mismatch error is around 1 5 The switched reference voltage device h...

Page 874: ...Instruments Incorporated Analog To Digital Converter ADC Module Figure 22 14 Mid point Value Calculation 22 2 6 2 ADC Self Test Mode The ADC module supports a self test mode which can be used to detec...

Page 875: ...ches refer to Figure 22 15 Table 22 3 Self Test Reference Voltages 1 SELF_TEST HILO S1 S2 S3 S4 S5 Reference Voltage 1 0 0 1 1 0 1 ADREFLO via R1 R2 connected to Vin 1 1 1 0 0 1 1 ADREFHI via R1 R2 co...

Page 876: ...nnel Condition Normal Conversion Result Vn Self test Conversion Result Vu Self test Conversion Result Vd Pin Condition Vn Vn Vu ADREFHI ADREFLO Vd Vn Good ADREFHI ADREFHI approx ADREFHI Shorted to ADR...

Page 877: ...put channel and the application software has to take account of this required delay 22 2 6 3 3 Managing Clocks to the ADC Module The clock to the ADC module can be turned off via the appropriate Perip...

Page 878: ...reads and writes are allowed to the ADC results RAM in this test mode NOTE Contention on access to ADC Results RAM The ADC module cannot handle a contention between the application write to the resul...

Page 879: ...ation 879 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Analog To Digital Converter ADC Module Figure 22 18 ADC Memory Map in Parity Test Mode 22 2 8...

Page 880: ...sabled depending on bit PDIS in the pull disable register ADEVTPDIS Output buffer The ADxEVT pin can be driven as an output pin if the ADEVTDIR bit is set in the pin direction control register Open Dr...

Page 881: ...terrupt Flag Register Section 22 3 15 3Ch ADG2INTFLG ADC Group2 Interrupt Flag Register Section 22 3 16 40h ADEVTHRINTCR ADC Event Group Threshold Interrupt Control Register Section 22 3 17 44h ADG1TH...

Page 882: ...GINTENACLR ADC Magnitude Compare Interrupt Enable Clear Register Section 22 3 57 160h ADMAGINTFLG ADC Magnitude Compare Interrupt Flag Register Section 22 3 58 164h ADMAGINTOFF ADC Magnitude Compare I...

Page 883: ...ernal state machines and the control status registers are reset 22 3 2 ADC Operating Mode Control Register ADOPMODECR Figure 22 21 and Table 22 8 describe the ADOPMODECR register Figure 22 21 ADC Oper...

Page 884: ...ode is enabled The application can directly write to the ADC RAM by the CPU or the DMA 15 9 Reserved 0 Reads return 0 Writes have no effect 8 POWERDOWN ADC Power Down This bit powers down only the ADC...

Page 885: ...r value for the ADC core clock ADCLK The ADCLK is generated by dividing down the input bus clock VCLK to the ADC module Note The supported range for the ADC clock frequency is specified in the device...

Page 886: ...libration conversion 15 10 Reserved 0 Reads return 0 Writes have no effect 9 BRIDGE_EN Bridge Enable When set with the HILO bit BRIDGE_EN allows a reference voltage to be converted in calibration mode...

Page 887: ...re 22 24 12 bit ADC Event Group Operating Mode Control Register ADEVMODECR offset 10h 31 24 Reserved R 0 23 17 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved EV_DATA_FMT R 0 R W 0 7 6 5 4...

Page 888: ...e 8 bit conversion result 3h Reserved The full 12 bit conversion result is returned if programmed EV_CHID Enable Channel Id for the Event Group conversion results to be read This bit only affects the...

Page 889: ...tinuously when the selected event trigger condition occurs FRZ_EV Event Group Freeze Enable This bit allows an Event Group conversion sequence to be frozen if a Group1 or a Group2 conversion is reques...

Page 890: ...2 bit ADC Group1 Operating Mode Control Register ADG1MODECR offset 14h 31 24 Reserved R 0 23 17 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved G1_DATA_FMT R 0 R W 0 7 6 5 4 3 2 1 0 Reserv...

Page 891: ...are returned as the 8 bit conversion result 3h Reserved The full 12 bit conversion result is returned if programmed G1_CHID Enable Channel Id for the Group1 conversion results to be read This bit only...

Page 892: ...G1_MODE Group1 Conversion Mode This bit defines whether the input channels selected for conversion in the Group1 are converted only once or are continuously converted Any operation mode read write 0...

Page 893: ...12 bit ADC Group2 Operating Mode Control Register ADG2MODECR offset 18h 31 24 Reserved R 0 23 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved G2_DATA_FMT R 0 R W 0 7 6 5 4 3 2 1 0 Reserved...

Page 894: ...are returned as the 8 bit conversion result 3h Reserved The full 12 bit conversion result is returned if programmed G2_CHID Enable Channel Id for the Group2 conversion results to be read This bit onl...

Page 895: ...e G2_MODE Group2 Conversion Mode This bit defines whether the input channels selected for conversion in the Group2 are converted only once or are continuously converted Any operation mode read write 0...

Page 896: ...bit configures the event group to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon detecting a...

Page 897: ...This bit configures the group1 to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon detecting...

Page 898: ...t This bit configures the group2 to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon detecting...

Page 899: ...nerated when conversion of all the channels selected for conversion in the Event Group is done 1 An Event Group conversion end interrupt is generated when conversion of all the channels selected for c...

Page 900: ...d write 0 No interrupt is generated when conversion of all the channels selected for conversion in the Group1 is done 1 A Group1 conversion end interrupt is generated when conversion of all the channe...

Page 901: ...d write 0 No interrupt is generated when conversion of all the channels selected for conversion in the Group2 is done 1 A Group2 conversion end interrupt is generated when conversion of all the channe...

Page 902: ...nt Group conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Event Group s...

Page 903: ...verted A Group1 conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Group1...

Page 904: ...verted A Group2 conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Group2...

Page 905: ...n if new conversion results are not allowed to overwrite the existing memory contents then the Event Group threshold counter is not decremented Refer to Section 22 2 3 2 for more details on the thresh...

Page 906: ...bits always read the same as G2_THR bit 8 of this register 8 0 G2_THR Group2 Threshold Counter Before ADC conversions begin on the Group2 this field is initialized to the number of conversion results...

Page 907: ...eshold Control Register and the EV_BLOCKS field of the Event Group DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if EV_BLK_XFER is set to 1 1h 1FFh One...

Page 908: ...r ADEVDMACR Field Descriptions continued Bit Field Value Description 0 EV_DMA_EN Event Group DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes the...

Page 909: ...hreshold Control Register and the G1_BLOCKS field of the Group1 DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if G1_BLK_XFER is set to 1 1h 1FFh One DMA...

Page 910: ...gister ADG1DMACR Field Descriptions continued Bit Field Value Description 0 G1_DMA_EN Group1 DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes the...

Page 911: ...hreshold Control Register and the G2 BLOCKS field of the Group2 DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if G2_BLK_XFER is set to 1 1h 1FFh One DMA...

Page 912: ...gister ADG2DMACR Field Descriptions continued Bit Field Value Description 0 G2_DMA_EN Group2 DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes the...

Page 913: ...ults The memory available is specified in terms of pairs of result buffers Any operation mode read write 0 Event Group conversions are not required If Event Group conversions are performed with the BN...

Page 914: ...on of the ADC results memory then the ADC results memory has been completely initialized to zeros For devices requiring parity checking on the ADC results memory the parity bit in the results memory w...

Page 915: ...This needs to be assured by configuring the EV_ACQ value properly considering the frequency of the ADCLK signal Refer to the device datasheet to determine the minimum sampling time for this device 22...

Page 916: ...22 33 ADC Group2 Sampling Time Configuration Register ADG2SAMP Field Descriptions Bit Field Value Description 31 12 Reserved 0 Reads return 0 Writes have no effect 11 0 G2_ACQ Group2 Acquisition Time...

Page 917: ...esults memory is empty or does not contain any unread conversion results 2 EV_BUSY Event Group Conversion Busy Any operation mode read 0 Event Group conversions are neither in progress nor frozen 1 Ev...

Page 918: ...e Group1 results memory is empty or does not contain any unread conversion results 2 G1_BUSY Group1 Conversion Busy Any operation mode read 0 Group1 conversions are neither in progress nor frozen 1 Gr...

Page 919: ...e Group2 results memory is empty or does not contain any unread conversion results 2 G2_BUSY Group2 Conversion Busy Any operation mode read 0 Group2 conversions are neither in progress nor frozen 1 Gr...

Page 920: ...on This also causes the ADC Event Group Results Memory pointer to be reset so that the memory allocated for storing the Event Group conversion results gets overwritten Care should be taken to re progr...

Page 921: ...tion This also causes the ADC Group1 Results Memory pointer to be reset so that the memory allocated for storing the Group1 conversion results gets overwritten Care should be taken to re program the c...

Page 922: ...tion This also causes the ADC Group2 Results Memory pointer to be reset so that the memory allocated for storing the Group2 conversion results gets overwritten Care should be taken to re program the c...

Page 923: ...R ADC Calibration Result and Offset Error Correction Value The ADC module writes the results of the calibration conversions to this register The application is required to use these conversion results...

Page 924: ...ons Bit Field Value Description 31 24 Reserved 0 Reads return 0 Writes have no effect 23 0 LAST_CONV ADC Input Channel s Last Converted Value This register indicates whether the last converted value f...

Page 925: ...ption Reserved 0 Reads return 0 Writes have no effect EV_EMPTY Event Group FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Event Group conversion results An...

Page 926: ...alue Description Reserved 0 Reads return 0 Writes have no effect G1_EMPTY Group1 FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Group1 conversion results A...

Page 927: ...alue Description Reserved 0 Reads return 0 Writes have no effect G2_EMPTY Group2 FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Group2 conversion results A...

Page 928: ...ead only n value after reset U value after reset is unknown Table 22 46 ADC Event Group Results Emulation FIFO Register ADEVEMUBUFFER Field Descriptions Field Value Description Reserved 0 Reads return...

Page 929: ...Read only n value after reset U value after reset is unknown Table 22 47 ADC Group1 Results Emulation FIFO Register ADG1EMUBUFFER Field Descriptions Field Value Description Reserved 0 Reads return 0...

Page 930: ...Read only n value after reset U value after reset is unknown Table 22 48 ADC Group2 Results Emulation FIFO Register ADG2EMUBUFFER Field Descriptions Field Value Description Reserved 0 Reads return 0...

Page 931: ...in Table 22 49 Figure 22 72 ADC ADEVT Pin Direction Control Register ADEVTDIR offset FCh 31 1 0 Reserved ADEVT_DIR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 49 ADC ADEVT...

Page 932: ...lue This bit determines the logic level to be output to the ADEVT pin when the pin is configured to be an output pin Any operating mode read write 0 Output logic LOW on the ADEVT pin 1 Output logic HI...

Page 933: ...s returns the current state of the ADEVT pin Any operating mode read write 0 Output value on the ADEVT pin is unchanged 1 Output logic HIGH on the ADEVT pin if the pin is configured to be an output pi...

Page 934: ...ADEVT pin if it is configured to be an output and a logic HIGH is being driven on to the pin Any operating mode read write 0 Output value on the ADEVT pin is logic HIGH 1 The ADEVT pin is tristated 2...

Page 935: ...ster ADEVSAMPDISEN is shown in Figure 22 80 and described in Table 22 57 Figure 22 80 ADC Event Group Sample Cap Discharge Control Register ADEVSAMPDISEN offset 11Ch 31 16 Reserved R 0 15 8 7 1 0 EV_S...

Page 936: ...ter ADG1SAMPDISEN Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 G1_SAMP_DIS_CYC Group1 sample cap discharge cycles These bits specify the du...

Page 937: ...ter ADG2SAMPDISEN Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return 0 Writes have no effect 15 8 G2_SAMP_DIS_CYC Group2 sample cap discharge cycles These bits specify the du...

Page 938: ...rts up to three magnitude compare interrupts These registers are at offset addresses 128h 130h and 138h Figure 22 83 12 bit ADC Magnitude Compare Interrupt Control Registers ADMAGINTxCR offset 128h 13...

Page 939: ...mpared with the MAG_CHIDx channel s conversion result CHN_THR_COMPx Channel OR Threshold comparison Any operation mode read write 0 The ADC module will compare the MAG_CHIDx channel s conversion resul...

Page 940: ...nd 13Ch Figure 22 85 12 bit ADC Magnitude Compare Mask Register ADMAGINTxMASK offset 12Ch 13Ch 31 12 11 0 Reserved MAG_INTx_MASK R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure...

Page 941: ...on mode read write for each bit 0 The enable status of the corresponding magnitude compare interrupt is left unchanged 1 The corresponding magnitude compare interrupt is enabled 22 3 57 ADC Magnitude...

Page 942: ...ite The corresponding flag is cleared The flag can also be cleared by reading from the magnitude compare interrupt offset register 22 3 59 ADC Magnitude Compare Interrupt Offset Register ADMAGINTOFF A...

Page 943: ...needs the Event Group memory to always be overwritten with the latest available conversion results then the OVR_EV_RAM_IGN bit in the Event Group operating mode control register ADEVMODECR needs to be...

Page 944: ...As a result the G2_FIFO_RESET bit will always be read as a 0 The G2_FIFO_RESET bit will only have the desired effect when the Group2 results memory is in an overrun condition It must be used when the...

Page 945: ...be stored This is specified in terms of the buffer number The application can read this register to determine the number of valid Group1 conversion results available until that time 22 3 65 ADC Group2...

Page 946: ...ield Descriptions Bit Field Value Description 31 9 Reserved 0 Reads return 0 Writes have no effect 8 TEST This bit maps the parity bits into the ADC results RAM frame so that the application can acces...

Page 947: ...enerated in the ADC results RAM This error address is frozen from being updated until it is read by the application In emulation mode this address is maintained frozen even when read 1 0 Reserved 0 Re...

Page 948: ...Ah to this field has no effect on the selected channel selection mode for the Event group and the ADC module continues to use the channel selection mode that was previously programmed channel selectio...

Page 949: ...return 0 Writes have no effect 3 0 G2_ENH_CHNSEL_ MODE_ENABLE Enable enhanced channel selection mode for Group2 Refer to Section 22 2 2 2 2 for a description of the enhanced channel selection mode 5h...

Page 950: ...l reset occurs An ADC software reset occurs via the ADC Reset Control Register ADRSTCR EV_CURRENT_COUNT becomes equal to EV_MAX_COUNT Application writes zeros to ADEVCURRCOUNT register Event group s r...

Page 951: ...ripheral reset occurs An ADC software reset occurs via the ADC Reset Control Register ADRSTCR G1_CURRENT_COUNT becomes equal to G1_MAX_COUNT Application writes zeros to ADG1CURRCOUNT register Group1 s...

Page 952: ...ripheral reset occurs An ADC software reset occurs via the ADC Reset Control Register ADRSTCR G2_CURRENT_COUNT becomes equal to G2_MAX_COUNT Application writes zeros to ADG2CURRCOUNT register Group2 s...

Page 953: ...ructions The N2HET micromachine is connected to a port of up to 32 input output I O pins NOTE This chapter describes a superset implementation of the N2HET module that includes features and functional...

Page 954: ...memory with dedicated High End Timer Transfer Unit HTU or DMA Diagnostic capabilities with different loopback mechanisms and pin status readback functionality Hardware Angle Generator HWAG 23 1 2 Maj...

Page 955: ...solution prescaler HETPFR 5 0 Loop resolution prescaler HETPFR 10 8 Register S Register T HR clock to IO PIN CONTROL HR clock CURRENT INSTRUCTION HOST INTERFACE N2HET RAM SPECIALIZED TIMER MICROMACHIN...

Page 956: ...ce The total timer program is a set of instructions executed sequentially one after the other Reaching the end the program must roll to the first instruction so that it behaves as a loop The time for...

Page 957: ...son conditions Two additional 32 bit temporary working registers R S New HETAND register for AND Sharing of High Resolution structure between pairs of pins Improved high resolution PCNT instruction 23...

Page 958: ...ized timer micromachine The host interface and I O control provide an interface to the CPU and external pins respectively 23 2 1 Specialized Timer Micromachine The N2HET has its own instruction set de...

Page 959: ...rity 2 T o VIM Rotate Shift By N HETADDR 8 0 HETPRY 31 0 From N2HET RAM To I O Control Register T Register S CURRENT INSTRUCTION PROGRAM FIELD CONTROL FIELD DATA FIELD www ti com N2HET Functional Desc...

Page 960: ...s prefetched The program execution begins at the occurrence of the loop resolution clock and continues executing the instructions until the program branches to 00h location The instruction is prefetch...

Page 961: ...cutes linearly NOTE While it would be unusual to code an N2HET program that is only one instruction long it is trivial to modify such a program to meet the requirement of restriction 1 Simply add a se...

Page 962: ...nect to the device that has been already programmed with the N2HET code that needs to debugged downloading to on chip flash is outside the scope of this section 3 Execute the CPU program at least unti...

Page 963: ...o The N2HET will automatically start executing when it sees that the CPU has exited the debug state Figure 23 6 Debug Control Configuration NOTE Consecutive break points are not supported Instructions...

Page 964: ...et while the N2HET is executing from on the same address See Section 23 2 4 3 Except for the case of automatic read clear the external host is stalled when the host and N2HET have a bank conflict Howe...

Page 965: ...field whereby each is 32 bit wide So when fetching N2HET instructions parity checking is performed on three words in parallel If a parity error is detected in two or more words in the same cycle then...

Page 966: ...nitialized With parity enabled the N2HET parity RAM will be initialized automatically by N2HET at the same time that the N2HET instruction RAM is initialized by the CPU Note that loading the N2HET pro...

Page 967: ...me slots VCLK2 cycles required to complete the worst case execution path through the N2HET program Otherwise a program overflow condition may occur see Section 23 2 1 4 Because of the relationship of...

Page 968: ...an LRP within one N2HET loop LRP The last section showed that LRP lr HRP There are lr high resolution clock periods HRP within the N2HET loop resolution clock period LRP If lr 128 then the HR delay c...

Page 969: ...HET RAM In general a 64 bit read access of one master could be interrupted by a 64 bit read access of another master A total of three shadow registers are available Therefore up to three masters can p...

Page 970: ...r the CPU accesses to the timer RAM or control registers are freely executed Ignore suspend The timer RAM ignores the suspend signal and operates real time as normal 23 2 4 5 Power Down After setting...

Page 971: ...hich avoids the possible coherency problem of the read modify write approach Coding Example C program Set pins using the 2 methods unsigned int MASK Variable that content the bit mask volatile unsigne...

Page 972: ...the next loop resolution cycle the Z flag is evaluated and the opposite pin action is performed if it is set The Z flag will only be active for one loop resolution cycle Figure 23 10 Loop Resolution...

Page 973: ...nchronized to the next loop resolution cycle which HR function to perform and on which edges it should take an action with the information given by the instruction The HR structure for each pin decode...

Page 974: ...es N and N 1 are connected to pin N In this structure pin N 1 remains available for general purpose input output See Figure 23 12 Figure 23 12 Example of HR Structure Sharing for N2HET Pins 0 1 The fo...

Page 975: ...1 remains available for general purpose input output Figure 23 13 XOR shared HR I O The following N2HET program gives an example for one channel of the symmetrical PWM The generated timing is given in...

Page 976: ...T instruction needs to be set to the period of the symmetric counter The next two waveforms HR 0 and HR 1 show the output of the HR structures which are the inputs for the XOR gate to create the PWM o...

Page 977: ...back between the two structures in the structure pair is determined by the value of LBPDIR x in the HETLBPDIR Register For example if bit LBPSEL 0 is set to 1 then HR structures 0 and 1 will be intern...

Page 978: ...loopback mode the structure pairs are connected outside of the output buffers Therefore the loopback values WILL be seen on the corresponding pins Figure 23 17 shows an example of analog loopback bet...

Page 979: ...s Actual limitations will be slightly different due to on chip routing and IO buffer delays usually by several nanoseconds Be sure to consult the device datasheet for actual timings that apply to that...

Page 980: ...100000b Shifting this value right by 5 bits results in 10b which equals the two HR clock cycles delay mentioned above Figure 23 19 ECMP Execution Timings HETPFR 31 0 register 0x201 lr 4 and hr 2 ts 8...

Page 981: ...5 11 Pulse Generation Example in HR Mode The PWCNT instruction may also be used in HR mode to generate pulse outputs with HR width It generates a single pulse when the data field of the instruction is...

Page 982: ...t 2018 Texas Instruments Incorporated High End Timer N2HET Module Figure 23 21 shows what happens when the capture edge arrives after the HR counter overflows This causes the incremented value to be c...

Page 983: ...r is captured in the HR capture register and written into the RAM after the next WCAP execution The WCAP instruction effectively time stamps the free running timer saved in a register for example regi...

Page 984: ...pull up if the bit in the N2HET Pull Select Register HETPSL is cleared the pin will have a pull down If the bit in the N2HET Pull Disable Register HETPULDIS is set there is no pull up or pull down on...

Page 985: ...0 Disabled Disabled Disabled No 0 1 1 Disabled Disabled Enabled No 1 X X Disabled Enabled Enabled 23 2 5 15 Open Drain Feature The following apply if the open drain feature is enabled on a pin that i...

Page 986: ...ETDIN register of the GIO pin that the level on nDIS is inactive high Software sets bit HET_PIN_ENA to deactivate the high impedance state of the pins 23 2 6 Suppression Filters Each N2HET pin is equi...

Page 987: ...e address code for this flag is determined by the five LSBs of the current timer program address The flag in the N2HET Interrupt Flag Register HETFLG is set even if the corresponding bit in the N2HET...

Page 988: ...ciated with a priority level level 1 or level 2 When multiple interrupts with the same priority level occur during the same loop resolution the lowest flag bit is serviced first In addition to the int...

Page 989: ...set vector T o Vectored Interrupt Manager PL bit 0 SW Int flag 0 PL bit 1 SW Int flag 1 PL bit 23 SW Int flag 23 PL bit 24 SW Int flag 24 PL bit 31 SW Int flag 31 PL bit 34 ExcInt En 2 ExcInt flag 2 w...

Page 990: ...HTUREQ x or both signals shown in Figure 23 29 The request line number x corresponds to the reqnum parameter used in the instruction Figure 23 29 Request Line Assignment Example 23 3 Angle Functions...

Page 991: ...Functions 991 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated High End Timer N2HET Module Figure 23 30 Operation of N2HET Count Instructions Due to ste...

Page 992: ...ons of the external signal measured by APCNT and compensates related counting errors A period increase is flagged in the deceleration flag A period decrease is flagged in the acceleration flag If no v...

Page 993: ...ference signal can be masked The start and end of singularities are defined by gap start and gap end values specified in SCNT and ACNT When ACNT reaches gap start or gap end it sets resets the gap fla...

Page 994: ...period value accidentally falls below the minimum allowed APCNT stops the capture of these periods and sets the APCNT underflow interrupt flag located in the exceptions interrupt control register In...

Page 995: ...used has 60 teeth with 6 tooth the period between two tooth edges interpolates the angle value and the step width gives the number of interpolated angles For an example of the angle generator principl...

Page 996: ...CPU HWAG Angle Tick Generation Noise Filtering HET Interface HWAG core 4 2 Angle Functions www ti com 996 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporate...

Page 997: ...which the HWAG global control register 2 HWAGCR2 defines as the falling or the rising edge of the input signal For an example of the angle tick generation principle see Figure 23 37 The speed of the t...

Page 998: ...signal The gap flag signal which changes the behavior of the HWAG during the singularity and resets the TCNT on the next active edge of the toothed wheel input The PCNT calculates the period P n betw...

Page 999: ...Instruments Incorporated High End Timer N2HET Module Figure 23 39 Angle Generation Using Time Based Algorithm Because of stepping the final count of the SCNT will usually be unequal to the target valu...

Page 1000: ...icks like for a normal tooth but with three times the value To generate these angle ticks the HWAG uses a constant period based on the previous tooth period Because the period is based on the previous...

Page 1001: ...cause the Gap flag 1 The tick counter is not reloaded because the Criteria flag is raised If PCNT n 2 x PCNT n 1 and the Gap flag 1 then the Criteria flag is raised The Gap flag and tooth active edge...

Page 1002: ...e corresponding interrupt you can also use the wired criteria When researching which algorithm to apply the counters ACNT and TCNT are frozen and must be initialized to their start values The ACNT val...

Page 1003: ...subroutine in code using the PCNT n 2 PCNT n 3 PCNT n 1 algorithm Figure 23 44 Code 23 3 2 2 3 Stopping the HWAG The HWAG starts synchronously with the active edge of the toothed wheel but stops when...

Page 1004: ...ftware must recover from such an interrupt to keep the HWAG operating optimally For an example of gap verification criteria for a 60 2 toothed wheel see Figure 23 45 Figure 23 45 Gap Verification Crit...

Page 1005: ...the ACNT must be reset when it reaches the angle zero point To reset the ACNT when it reaches the angle zero point set the ARST bit to 1 Setting the ARST bit before the reload of the tick counter wil...

Page 1006: ...ounter The value of the remaining percentage of the tick counter 1 X need to be set because the tick counter is a down counter Calculate the value to put into the filter registers from the step width...

Page 1007: ...s When conditions are set the HWAG interrupts are generated When the interrupt condition is true the corresponding flag is set in the HWAG interrupt flag register HWAFLG If the corresponding enable bi...

Page 1008: ...rmation on these interrupts see Table 23 14 Each interrupt source is associated with a low or high priority When one or more interrupts with the same priority occur a fixed priority determines the off...

Page 1009: ...ious one when the HWAG expects a normal tooth This interrupt can detect the singularity without bit manipulation by the CPU Bad active edge tooth This interrupt indicates that an active edge has occur...

Page 1010: ...high end timers This connection allows you to perform angle compare and angle time compare For an example of the hardware angle generator high end timer interface see Figure 23 50 Figure 23 50 Hardwar...

Page 1011: ...tion The NHET can then implement its own angle counter using a CNT instruction in angle mode which will be incremented once per resolution by the value given by the angle increment For an example of a...

Page 1012: ...P instruction performs an in between comparison old angle value compare value new angle value to match the position of the toothed wheel This instruction where an equality compare executes every resol...

Page 1013: ...ed to 1 23 3 2 4 3 2 HWAG to NHET Interface The NHET interface is a 11 bit counter sampled by the NHET and reset by the NHET resolution The counter contains the value of ACNT incremented during the la...

Page 1014: ...ven SYSCLK RPM minimum is related to PCNT overflow and SYSCLK Maximum PCNT value SYSCLK Maximum tooth period PCNT is a 24 bit counter based on SYSCLK RPM maximum is related to the angle step and SYSCL...

Page 1015: ...maximum angle accuracy is a function of the angle step and the NHET loop resolution The increment per resolution limits the interface between the HWAG and the NHET The maximum angle increment per NHE...

Page 1016: ...the next falling edge Because of this compensation the NHET interface will not overflow and fewer errors will occur on the NHET angle counter in case of strong acceleration NOTE Reading the angle incr...

Page 1017: ...4 11 2Ch HETAND AND Share Control Register Section 23 4 12 34h HETHRSH HR Share Control Register Section 23 4 13 38h HETXOR HR XOR Share Control Register Section 23 4 14 3Ch HETREQENS Request Enable...

Page 1018: ...HET RAM between the HET Transfer Unit and another arbiter which outputs the access of one of the remaining masters The MP bits allow the following selections 0 The HTU has lower priority to access the...

Page 1019: ...served 0 Reads return 0 Writes have no effect 0 TO Turn On Off TO does not affect the state of the pins You must set reset the timer pins when they are turned off or re initialize the timer RAM and co...

Page 1020: ...0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 23 17 Prescale Factor Register HETPFR Field Descriptions Bit Field Value Description 31 11 Reserved 0 Rea...

Page 1021: ...address Write Writes have no effect 23 4 4 Offset Index Priority Level 1 Register HETOFF1 N2HET1 offset FFF7 B80Ch N2HET2 offset FFF7 B90Ch Figure 23 59 Offset Index Priority Level 1 Register HETOFF1...

Page 1022: ...10h Figure 23 60 Offset Index Priority Level 2 Register HETOFF2 31 16 Reserved R 0 15 6 5 0 Reserved OFFSET2 R 0 R 0 LEGEND R Read only n value after reset Table 23 21 Offset Index Priority Level 2 Re...

Page 1023: ...ruction set Writing a 0 to HETINTENAS has no effect When reading from HETINTENAS bit x gives the information if N2HET instructions x 0 x 32 x 64 and so on have the interrupt enabled or disabled 0 Read...

Page 1024: ...es have no effect 24 APCNT_OVRFL_ENA APCNT Overflow Enable 0 APCNT overflow exception is not enabled 1 Enables the APCNT overflow exception 23 17 Reserved 0 Reads return 0 Writes have no effect 16 APC...

Page 1025: ...pped at a breakpoint Also generates a debug request to halt the ARM CPU 0 Read N2HET is either running or stopped flag cleared but not yet restarted Write No effect 1 Read N2HET is stopped at a breakp...

Page 1026: ...te R Read only W1C Write 1 to clear n value after reset X Unknown Table 23 27 Interrupt Flag Register HETFLG Field Descriptions Bit Field Value Description 31 0 HETFLAG n Interrupt Flag Register Bits...

Page 1027: ...8 AND SHARE7 6 AND SHARE5 4 AND SHARE3 2 AND SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 28 AND Share Control Register HETA...

Page 1028: ...HR SHARE9 8 HR SHARE7 6 HR SHARE5 4 HR SHARE3 2 HR SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 29 HR Share Control Register...

Page 1029: ...8 XOR SHARE7 6 XOR SHARE5 4 XOR SHARE3 2 XOR SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 30 XOR Share Control Register HETXO...

Page 1030: ...ine n Note The request line can trigger a DMA control packet DMA channel an HTU double control packet DCP or both simultaneously The HETREQDS register determines to which module s the N2HET request li...

Page 1031: ...ly n value after reset Table 23 33 Request Destination Select Register HETREQDS Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reads return 0 Writes have no effect 23 16 TDBSn HTU DMA...

Page 1032: ...Figure 23 73 N2HET Direction Register HETDIR 31 16 HETDIR R W 0 15 0 HETDIR R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 34 N2HET Direction Register HETDIR Field Descriptions...

Page 1033: ...at logic low 0 1 Pin HET n is at logic high 1 23 4 20 N2HET Data Output Register HETDOUT N2HET1 offset FFF7 B854h N2HET2 offset FFF7 B954h Figure 23 75 N2HET Data Output Register HETDOUT 31 16 HETDOU...

Page 1034: ...as logic 0 leave the same bit in HETDOUT unchanged Reads from this address return the value of the HETDOUT register 0 Write HETDOUT n is unchanged 1 Write HETDOUT n is set 23 4 22 N2HET Data Clear Re...

Page 1035: ...te of the output buffer HETDOUT n 0 The output buffer of pin HET n is driven low HETDOUT n 1 The output buffer of pin HET n is tristated 23 4 24 N2HET Pull Disable Register HETPULDIS Values in this re...

Page 1036: ...DIS is 0 1 The pull up functionality is enabled if corresponding bit in HETPULDIS is 0 NOTE See device data sheet for which pins provide programmable pullups pulldowns Table 23 9 shows how the registe...

Page 1037: ...effect 8 TEST Test Bit When this bit is set the parity bits are mapped into the peripheral RAM frame to make them accessible by the CPU 0 Read Parity bits are not memory mapped Write Disable mapping 1...

Page 1038: ...ds the offset address of the first parity error which is detected in N2HET RAM This error address is frozen from being updated until it is read by the CPU During emulation mode this address is frozen...

Page 1039: ...s Bit Field Value Description 31 0 HETPPR n NHET Parity Pin Select Bits Allows HET n pins to be configured to drive to a known state when an N2HET parity error is detected 0 Pin HET n is not affected...

Page 1040: ...k and VCLK2 0 CCLK VCLK2 1h CCLK VCLK2 2 2h CCLK VCLK2 3 3h CCLK VCLK2 4 15 10 Reserved 0 Reads return 0 Writes have no effect 9 0 CPRLD Counter Preload Value CPRLD contains the preload value for the...

Page 1041: ...19 18 LBPSEL17 16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 LBPSEL15 14 LBPSEL13 12 LBPSEL11 10 LBPSEL9 8 LBPSEL7 6 LBPSEL5 4 LBPSEL3 2 LBPSEL1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R...

Page 1042: ...13 12 LBPDIR11 10 LBPDIR9 8 LBPDIR7 6 LBPDIR5 4 LBPDIR3 2 LBPDIR1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after res...

Page 1043: ...ister HETPINDIS 31 16 HETPINDIS R W 0 15 0 HETPINDIS R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 50 NHET Pin Disable Register HETPINDIS Field Descriptions Bit Field Value Desc...

Page 1044: ...23 5 6 B4h HWALVLSET HWAG Interrupt Level Set Register Section 23 5 7 B8h HWALVLCLR HWAG Interrupt Level Clear Register Section 23 5 8 BCh HWAFLG HWAG Interrupt Flag Register Section 23 5 9 C0h HWAOFF...

Page 1045: ...value after reset Table 23 52 HWAG Pin Select Register HWAPINSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reads return 0 Writes have no effect 4 0 PINSEL HWAG Pin Select Selects...

Page 1046: ...return 0 Writes have no effect 0 RESET HWAG Module Reset 0 HWAG module is reset 1 HWAG module is not in reset 23 5 3 HWAG Global Control Register 1 HWAGCR1 Figure 23 91 HWAG Global Control Register 1...

Page 1047: ...HWAG generates an interruption singularity not found if the interrupt is enabled 0 Do not reset ACNT once it reaches the angle zero point 1 Reset ACNT once it reaches the angle zero point 23 18 Reser...

Page 1048: ...R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 56 HWAG Interrupt Enable Set Register HWAENASET Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Write...

Page 1049: ...A6 CLRINTENA5 CLRINTENA4 CLRINTENA3 CLRINTENA2 CLRINTENA1 CLRINTENA0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 58 HWAG Interrupt En...

Page 1050: ...effect 7 0 SETINTLVL n Set Interrupt Level See Table 23 57 0 Read Low priority interrupt Write No effect 1 Read High priority interrupt Write Set interrupt priority to high 23 5 8 HWAG Interrupt Leve...

Page 1051: ...escription 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 INTFLG n Interrupt Flag These bit are set when an interrupt condition has occurred inside the HWAG The interrupt is sent to the CPU...

Page 1052: ...register is the bit for which the corresponding interrupt enable bit is set During suspend mode a read to this register does not clear the corresponding interrupt bit Figure 23 98 HWAG Interrupt Offs...

Page 1053: ...register is the bit for which the corresponding interrupt enable bit is set During suspend mode a read to this register does not clear the corresponding interrupt bit Figure 23 99 HWAG Interrupt Offs...

Page 1054: ...AG Angle Value Register HWAACNT 31 24 23 16 Reserved ACNT R 0 R W 0 15 0 ACNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 23 64 HWAG Angle Value Register HWAACNT Field Descriptio...

Page 1055: ...Fh Period n 1 Value Gives the period value of the previous tooth 23 5 14 HWAG Current Tooth Period Value Register HWAPCNT Figure 23 102 HWAG Current Tooth Period Value Register HWAPCNT 31 24 23 16 Res...

Page 1056: ...D R W Read Write R Read only n value after reset Table 23 67 HWAG Step Width Register HWASTWD Field Descriptions Bit Field Value Description 31 4 Reserved Reads return 0 Writes have no effect 3 0 STWD...

Page 1057: ...1 8 Reserved 0 Reads return 0 Writes have no effect 7 0 THNB 0 FFh Teeth Number Sets the teeth number with the maximum value of the toothed wheel This must be equal to N 1 real teeth that is 57 for a...

Page 1058: ...th signal to be taken into account by the HWAG This function works only if the mode filtering is set The value is calculated as shown in Section 23 3 2 2 5 23 5 19 HWAG Filter Register 2 HWAFIL2 Figur...

Page 1059: ...t Register HWAANGI 31 16 Reserved R 0 15 10 9 0 Reserved ANGI R 0 R 0 LEGEND R Read only n value after reset Table 23 72 HWAG Angle Increment Register HWAANGI Field Descriptions Bit Field Value Descri...

Page 1060: ...rry and Shift 4h C 25 23 011 C5 1 1 3 ADD Add and Shift 4h C 25 23 001 C5 1 1 3 ADM32 Add Move 32 4h C 25 23 000 C5 1 1 2 AND Bitwise AND and Shift 4h C 25 23 010 C5 1 1 3 APCNT Angle Period Count Eh...

Page 1061: ...MP ACNT BR ECMP MCMP MOV32 RCNT SCMP SHFT X Angle Compare Match Flag ACMP SCMP SWF 0 1 Step Width flags SCNT ACNT NAF New Angle Flag ACNT NAF_global NAF_global New Angle Flag global HWAG or NAF ACMP B...

Page 1062: ...equest NOREQ request GENREQ and quiet request QUIET See Section 23 2 9 Default No request Location Control Field 28 27 Request C 28 C 27 To HTU To DMA NOREQ 0 0 no request no request 1 0 GENREQ 0 1 re...

Page 1063: ...ilable for ACMP ADC ADD ADM32 AND DADM64 ECMP ECNT MCMP MOV32 MOV64 OR RADM64 SBB SHFT SUB WCAP WCAPE instructions Register Ext Reg C 7 C 2 C 1 A 0 0 0 B 0 0 1 T 0 1 0 None 0 1 1 R 1 0 0 S 1 0 1 Reser...

Page 1064: ...A value of ON sets the previous pin level bit to 1 A value of OFF sets the initial value of the previous prv bit to 0 The prv bit is overwritten set or reset by the N2HET the first time the instructi...

Page 1065: ...ol OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number action CLEAR SET reg A B R S T NONE irq OFF ON data 25 bit unsigned integer Figure 23 109 ACMP Program Field P31 P0...

Page 1066: ...rupt is generated Specifying ON generates an interrupt when the edge state is satisfied and the gap flag is set Specifying OFF prevents an interrupt from being generated Default OFF data Specifies the...

Page 1067: ...24 0 Res Request type Control Prv Gap End 3 2 1 1 25 Figure 23 114 ACNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles Two as follows First cycle Angle increment condition and gap end comparison...

Page 1068: ...ge Select Rising 1 Detects a rising edge of HET 2 Falling 0 Detects a falling edge of HET 2 irq ON generates an interrupt when the edge state is satisfied and the gap flag is set OFF prevents an inter...

Page 1069: ...1 If specified edge is detected on pin HET 2 DCF 0 If target_edge_field 0 AND DCF 0 ACF 1 If GPF 1 GPF 0 Z 1 If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on req...

Page 1070: ...ure 23 116 ADCNST Control Field C31 C0 31 27 26 25 24 0 Reserved Control Res Minimum offset 5 1 1 25 Figure 23 117 ADCNST Data Field D31 D0 31 7 6 0 Data HR Data 25 7 Cycles Two Register modified Regi...

Page 1071: ...orated High End Timer N2HET Module Figure 23 118 and Figure 23 119 illustrate the behavior of ADCNST if the remote data field is zero or is not zero Figure 23 118 ADCNST Operation If Remote Data Field...

Page 1072: ...Control Sub Opcode Src1 Src2 5 1 3 4 3 15 13 12 8 7 6 5 4 3 2 1 0 Smode Scount Ext Reg Init flag 1 Rdest Register select Res 3 5 1 1 1 2 2 1 Figure 23 122 ADC ADD AND OR SBB SUB XOR Data Field D31 D0...

Page 1073: ...ration may be selected through the smode and scount operands The shift or rotate type is selected by the smode field Table 23 79 illustrates the options that are available for smode The number of bits...

Page 1074: ...is the updated carry flag after the shift operation is performed s is the sign bit Table 23 79 Shift Encoding Shift Type C 15 13 smode Operation Illustrated 1 No Shift Applied 0 0 0 n a no shift ASR A...

Page 1075: ...11 SRC1 31 0 0xFFFFFFFF case 1000 SRC1 31 0 Remote Data Field D 31 0 case 1001 SRC1 31 9 0 SRC1 8 0 Remote Program Field P 8 0 switch C18 C16 case 000 SRC2 31 0 0x00000000 case 001 SRC2 31 0 Immediate...

Page 1076: ...OR IR1 31 OR IV1 case 011 smode Carry Shift Left IR2 31 scount IR1 31 scount 0 if scount 0 IR2 scount 1 0 IC1 IC1 IC2 IR1 31 scount 1 else IC2 IC1 IN2 IR2 31 if IR2 0 IZ2 1 else IZ2 0 IV2 IR2 31 XOR I...

Page 1077: ...31 if IR2 0 IZ2 1 else IZ2 0 IV2 IR2 31 XOR IR1 31 OR IV1 WRITE REGISTER DESTINATION STAGE switch C7 C2 C1 case 000 A 24 0 IR2 31 8 case 001 B 24 0 IR2 31 8 case 010 T 31 0 IR2 31 0 case 011 IR2 is n...

Page 1078: ...000 Reserved 5 1 3 15 15 8 7 6 5 4 3 2 1 0 Reserved Ext Reg Init flag 1 Move type Register select Res 15 1 1 1 2 2 1 Figure 23 125 ADM32 Data Field D31 D0 31 7 6 0 Data HR Data 25 7 Cycles One or two...

Page 1079: ...R S or T Remote data field 1 If selected register is R S or T the operation is a 32 bit Addition move If A or B register is selected it is limited to 25 bit operation since A and B only support 25 bi...

Page 1080: ...B R S or T 32 bits LSBs HR data field 25 32 bit addition move HR HR HR dashed for R S T dashed for R S T Instruction Set www ti com 1080 SPNU563A March 2018 Submit Documentation Feedback Copyright 201...

Page 1081: ...1 1 25 Figure 23 130 APCNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles One or two cycles Cycle 1 edge detected normal operation Cycle 2 edge detected and GPF 1 and underflow condition is tru...

Page 1082: ...The edge select encoding is shown in Table 23 82 irq ON generates an interrupt when the edge state is satisfied OFF prevents an interrupt from being generated Default OFF type Specifies the edge type...

Page 1083: ...od count 1FFFFFFh elseIf GPF 0 AND Data Field register Step width Register A Data field register 1 Register T Register A Period count Register T If Interrupt Enable 1 HETFLG n 1 n depends on address I...

Page 1084: ...31 P0 31 26 25 23 22 21 13 12 9 8 0 0 Request Number BRK Next program address 1101 Reserved 6 3 1 9 4 9 Figure 23 132 BR Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Contro...

Page 1085: ...Q Z 0 0 1 0 1 Equal or Zero Z 1 NE NZ 0 0 1 1 1 Not Equal or Not Zero Z 0 N 0 1 0 0 1 Negative N 1 PZ 0 0 1 1 1 Positive or Zero N 0 V 0 1 1 0 1 Overflow V 1 NV 0 1 1 1 1 No Overflow V 0 ZN 1 0 0 0 1...

Page 1086: ...1 Figure 23 135 CNT Control Field C31 C0 31 29 28 27 26 25 24 0 Res Request type Control Res Max Count 3 2 1 1 25 Figure 23 136 CNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles One or two One...

Page 1087: ...et to EQ the counter is reset when it is equal to the maximum count When set to GE the counter is reset when it is greater or equal to the maximum count Default GE irq ON generates an interrupt when t...

Page 1088: ...3 If C28 C27 11 Generate quiet request on request line P25 P23 else Selected register Immediate Data Field Angle Increment Immediate Data Field Immediate Data Field Angle Increment else if Time mode b...

Page 1089: ...ed integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A B...

Page 1090: ...trol field at the remote address The remote data field value is not just replaced but is added with the DADM64 data field DADM64 has two distinct syntaxes In the first syntax bit values may be set by...

Page 1091: ...remote instruction action maintains the control field for the remote instruction irq maintains the control field for the remote instruction data Specifies the 25 bit initial value for the data field...

Page 1092: ...program address 1010 Res 10 Reserved 6 3 1 9 4 1 2 6 Figure 23 142 DJZ Control Field C31 C0 31 29 28 27 26 25 22 21 16 Reserved Request type Control Reserved Conditional address 3 2 1 4 9 15 13 12 8 7...

Page 1093: ...er value used as a counter This counter is decremented each time the DJZ instruction is executed until the counter reaches 0 Default 0 Execution If Data 0 Data Selected register Data 1 Jump to Next Pr...

Page 1094: ...er action CLEAR SET PULSELO PULSEHI reg A B R S T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 23 144 ECMP Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 0...

Page 1095: ...oop resolution clock If the hr_lr bit is set the delay is ignored This delay is programmed in the data field D6 D0 The behavior of the pins is governed by the four action options in bits C4 C3 ECMP us...

Page 1096: ...AT next loop resolution clock If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on request line P25 P23 If C28 C27 11 Generate quiet request on request line P25 P23...

Page 1097: ...2 21 16 Reserved Request type Control Prv Reserved Conditional address 3 2 1 1 3 9 15 13 12 8 7 6 4 3 2 1 0 Conditional address Pin select Ext Reg Event Res Register select Int ena 9 5 1 3 1 2 1 Figur...

Page 1098: ...tion N irq ON generates an interrupt when event in counter mode occurs No interrupt is generated with OFF Default OFF data 25 bit integer value serving as a counter Default 0 Execution If event occurs...

Page 1099: ...ET PULSELO PULSEHI reg A B R S T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 23 150 MCMP Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 5 4 0 0 Request Num...

Page 1100: ...ompare Values The difference between the two data values must not exceed 224 1 angle_comp Determines whether or not an angle compare is performed A value of ON causes the comparison to be performed on...

Page 1101: ...1 If hr_lr P 8 0 Schedule Action on Selected Pin C 12 8 at start of next loop HR Delay D 6 0 else Schedule Pin Action on Selected Pin C 12 8 at start of next loop If Interrupt Enable 1 HETFLG n 1 n de...

Page 1102: ...0100 Remote Address 6 3 1 9 4 9 Figure 23 154 MOV32 Control Field C31 C0 31 27 26 25 23 22 21 16 Reserved Control Reserved Z Fl Cond Reserved 5 1 3 1 14 15 8 7 6 5 4 3 2 1 0 Reserved Ext Reg Init flag...

Page 1103: ...angle flag NAF 0 A value of OFF results in no change to the system flags type Specifies the move type to be executed Table 23 87 Move Type Encoding Selection Move Type C4 C3 Source Destination s Cycl...

Page 1104: ...field 25 32 bit move Immediate DF Register A B R S or T Remote DF HR HR HR dashed for R S T Instruction Set www ti com 1104 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instr...

Page 1105: ...22 1 AND Z Flag 1 switch type C 4 3 case 00 IMTOREG Selected register Immediate Data Field case 01 IMTOREG REM Selected register Immediate Data Field Remote Data Field Immediate Data Field case 10 REG...

Page 1106: ...integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A B R...

Page 1107: ...t syntax bit values may be set by assigning a value to each of the control fields This syntax is convenient for modifying control fields that are arranged similarly to the format of the MOV64 control...

Page 1108: ...tains the control field for the remote instruction data Specifies the 25 bit initial count value for the data field If omitted the field defaults to 0 hr_data Optional HR delay The default value for a...

Page 1109: ...1 Int ena Type select hr_lr Pin select 6 3 1 9 4 1 2 1 5 Figure 23 165 PCNT Control Field C31 C0 31 29 28 27 26 25 24 0 Res Request type Control Prv Period Count 3 2 1 1 25 Figure 23 166 PCNT Data Fie...

Page 1110: ...ay Default 0 If period measure is selected PCNT captures the counter value into the period pulse data field D31 D7 on the selected edge The HR structure provides HR capture field D6 D0 The counter val...

Page 1111: ...ue 1FF_FFFFh HR Capture Value selected HR counter else HR Capture Value 7Fh If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on request line P25 P23 If C28 C27 11 G...

Page 1112: ...r action CLEAR SET PULSELO PULSEHI reg A B T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 23 167 PWCNT Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 5 0 0...

Page 1113: ...stays at zero until it is reloaded with a non zero value The specified pin action is performed as long as the count after count value is decremented is greater than 0 The opposite pin action is perfo...

Page 1114: ...Data field value 1 Selected register 0000000h Data field value 0000000h If Opposite action 1 If hr_lr bit 0 If Enable Pin action 1 Selected Pin Opposite level of Pin Action AT next loop resolution cl...

Page 1115: ...gned integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A...

Page 1116: ...is also the next address Register modified None Description This instruction modifies the data field the HR data field and the control field at the remote address The advantage over DADM64 is that It...

Page 1117: ...e instruction cond_addr Maintains the control field for the remote instruction pin Maintains the control field for the remote instruction register Maintains the control field for the remote instructio...

Page 1118: ...an input period measurement TInput to the form of Equation 31 where the input period is expressed as a fraction of a reference period TReference 31 RCNT computes the numerator N of Equation 31 The den...

Page 1119: ...struction detects a falling edge on pin 0 Between falling edges on pin0 RCNT accumulates counts 10x faster than PCNT so that the working data field of RCNT will reach the reference value of 0x400 in 1...

Page 1120: ...P Control Field C31 C0 31 29 28 27 26 25 24 23 22 21 16 Reserved Request type Control Cout prv Reserved En pin action Conditional address 3 2 1 1 2 1 9 15 13 12 8 7 6 5 4 3 2 1 0 Conditional address P...

Page 1121: ...nce the LSB of the conditional address is used to select between time mode and angle mode and since the conditional address is taken only in time mode the destination for the conditional address must...

Page 1122: ...ata Reserved 25 7 Cycles One or two cycles two cycles when DF is involved in the calculations Register modified Register A Description This instruction can be used only once in a program and defines a...

Page 1123: ...NT stored in register T The resulting period of SCNT is P n 1 K Due to stepping the final count of SCNT will not usually exactly match the target p n 1 SCNT compensates for this error by starting each...

Page 1124: ...umber BRK Next program address 1111 Reserved Smode 6 3 1 9 4 5 4 Figure 23 184 SHFT Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Control Prv Reserved Conditional address 3...

Page 1125: ...MSB 1st on HETx 1 into LSB ORZ 0 1 0 0 Shift Out Right LSB 1st on HETx Z into MSB OLZ 0 1 0 1 Shift Out Left MSB 1st on HETx Z into LSB IRM 1 0 0 0 Shift In Right HETx into MSB ILL 1 0 0 1 Shift In Le...

Page 1126: ...if P3 P0 1011 Z MSB of the Immediate Data Field If Immediate Data Field all 0 s OR Immediate Data Field all 1 s if Interrupt Enable 1 HETFLG n 1 n depends on address Jump to Conditional Address else J...

Page 1127: ...umber BRK Next program address 1011 hr_lr Reserved 6 3 1 9 4 1 8 Figure 23 187 WCAP Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Control Prv Reserved Conditional address 3...

Page 1128: ...synchronize to the next loop clock When N2HET is turned on and a capture edge occurs in the first loop clock where the HR counter hasn t been synchronized to the loop clock then the captured HR counte...

Page 1129: ...1 26 25 23 22 21 13 12 9 8 0 0 Request Number BRK Next program address 1000 Reserved 6 3 1 9 4 9 Figure 23 190 WCAPE Control Field C31 C0 31 29 28 27 26 25 24 23 22 21 16 Reserved Request type Control...

Page 1130: ...eger value for D31 D7 Default 0 ec_data Specifies the initial 7 bit integer value for D6 D0 Default 0 Execution If Specified Capture Condition is true on Selected Pin OR Unconditional capture is selec...

Page 1131: ...ized to transfer N2HET High End Timer data to or from the microcontroller RAM NOTE This chapter describes a superset implementation of the HTU module that includes features and functionality that requ...

Page 1132: ...to gather measurement data or creating output waveforms and thus freeing up the CPU to perform other tasks 24 1 1 Features Independently transfers data between the N2HET and the main memory 8 double...

Page 1133: ...t initiates transfers with the help of requests generated by the N2HET program and configurable control packets Figure 24 1 shows a system block diagram of the HTU and the main path for the data trans...

Page 1134: ...h the data is transferred This serves as memory protection in the case that information in the control packet RAM was unintentionally altered and avoids that the HTU can overwrite important applicatio...

Page 1135: ...1 24 2 1 2 Single Buffer Implementation In a single buffer implementation the DCP is set up to transfer data to from a single buffer in the main RAM With each transfer request the programmed number o...

Page 1136: ...20h 24h 3 2 1 28h 2Ch 30h end of buffer end of buffer 1 Buffer X 5 4 3 2 1 1 2 3 4 5 X X 15 14 13 12 11 10 9 8 15 15 15 15 15 15 7 6 5 4 3 2 1 TU request 1 Element Counter Element Number t1 t2 Increas...

Page 1137: ...double control packets DCPs supporting the use of two buffers per data stream per HTU request source If one buffer should be read by the CPU or DMA the data stream is directed to the other buffer and...

Page 1138: ...me t3 then the frame is processed by the new control packet although the old control packet was active at the time of the request The delays between the HTU requests and the start of the element trans...

Page 1139: ...nt the HTU modifying the main memory It could happen that a request was already active but the frame transfer hasn t started yet when the application disabled the control packets The timing diagram in...

Page 1140: ...stopped Accordingly the busy bit is cleared after the element which follows the element that caused the error In case of the Bus Error the counter for the element which follows the element that cause...

Page 1141: ...to the N2HET loop LRP in which the N2HET updates the data fields of the L1 L2 and L3 instructions In this case the HTU could read inconsistent data as shown in the diagram A wrong new value is read fr...

Page 1142: ...quest could also be used to define periods in which the data read by a control packet is safe The following HET code will capture counter time stamps to the L1 WCAP data field after rising edges at pi...

Page 1143: ...P x will not be affected 5 The FT flag will be set 6 An error is signaled to the ESM module 24 2 6 Control Packet RAM Parity Checking The HTU module can detect parity errors in the DCP Double Control...

Page 1144: ...memory Table 24 3 DCP RAM Bit 31 24 23 16 15 8 7 0 FF4E 0000h Byte 0 Byte 1 Byte 2 Byte 3 FF4E 0004h Byte 4 Byte 5 Byte 6 Byte 7 FF4E 0008h Byte 8 Byte 9 Byte 10 Byte 11 FF4E 000Ch Byte 12 Byte 13 By...

Page 1145: ...same PCNT instruction without loading or interrupting the CPU 24 3 2 Example Multiple Element Transfer with One Trigger Request The following example shows how the HTU could be used to fill a RAM buff...

Page 1146: ...t Counter 3 2 1 3 2 1 3 2 1 Source Address HET 38h 48h 58h 38h 48h 58h 38h 48h 58h Destination Address main CPU RAM 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h The destination buffer is filled with the WCAP E...

Page 1147: ...as shown on the right in Table 24 9 Table 24 9 Destination Buffer Values Address Frame Count Instruction Value 70h 3 WCAP Control Field Value 74h 3 WCAP 3 78h 3 ECNT Control Field Value 7Ch 3 ECNT 1...

Page 1148: ...and Bus Error Control Register Section 24 4 8 24h HTU BFINTS Buffer Full Interrupt Enable Set Register Section 24 4 9 28h HTU BFINTC Buffer Full Interrupt Enable Clear Register Section 24 4 10 2Ch HTU...

Page 1149: ...d to 0 and the parity functionality must be enabled by PARITY_ENA during the automatic DCP RAM initialization see Initializing Parity Bits If HTUEN is 1 when the initialization is triggered by the sys...

Page 1150: ...bled simultaneously 1 0 CP B is enabled and CP A are disabled simultaneously 1 1 CP B and CP A are both disabled simultaneously Table 24 14 CPENA Read Results Bit 2 x 1 Bit 2 x State of DCP 0 0 The DC...

Page 1151: ...y Flag for CP B of DCP 0 15 9 Reserved 0 Reads return 0 Writes have no effect 8 BUSY1A Busy Flag for CP A of DCP 1 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY1B Busy Flag for CP B of DC...

Page 1152: ...lag for CP B of DCP 2 15 9 Reserved 0 Reads return 0 Writes have no effect 8 BUSY3A Busy Flag for CP A of DCP 3 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY3B Busy Flag for CP B of DCP 3...

Page 1153: ...BUSY7A Busy Flag for CP A of DCP 7 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY7B Busy Flag for CP B of DCP 7 24 4 7 Active Control Packet and Error Register HTU ACPE Figure 24 20 Activ...

Page 1154: ...PN is frozen from being updated until the upper 16 bit word of the ACPE register or the complete 32 bit register is read by the CPU After this read the HTU will update ERRCPN if one of the above condi...

Page 1155: ...INTENA Bus Error Interrupt Enable Bit 0 The bus error interrupt is disabled for all DCPs 1 The bus error interrupt is enabled for all DCPs 15 9 Reserved 0 Reads return 0 Writes have no effect 8 CORL C...

Page 1156: ...er A is full that is once the frame counter CFTCTA decrements to 0 The same applies for CP B and CFTCTB 0 Interrupt is disabled Writing a 0 has no effect 1 Writing to bit 2 x enables the interrupt for...

Page 1157: ...ffect 16 MAPSEL Interrupt Mapping Select Bit 0 If MAPSEL is 0 then one bit of CPINTMAP selects one of two interrupt priorities 0 or 1 for the buffer full interrupt for the according CP The request los...

Page 1158: ...terrupt Line 0 Indicates whether a buffer full RLOST or BER interrupt assigned to interrupt line 0 is currently pending 0 No interrupt 1h Interrupt caused by full buffer on CP DCP specified by CPOFF0...

Page 1159: ...whether a buffer full RLOST or BER interrupt assigned to interrupt line 1 is currently pending 0 No interrupt 1h Interrupt caused by full buffer on CP DCP specified by CPOFF1 2h RLOST interrupt gener...

Page 1160: ...d A buffer is initialized In circular buffer transfer mode defined by TMBx when the end of the buffer is reached When CPs are switched or enabled according to Buffer Initialization The CPENA bits 2 x...

Page 1161: ...ed for the cases E and F and not for all the other cases shown in Table 24 27 Also when a buffer reaches its end in circular mode it uses the initial DCP information to restart independently of the BI...

Page 1162: ...er Full Interrupt Flag Register HTU BFINTFL offset 44h 31 16 Reserved R 0 15 0 BFINTFL R W1CP 0 LEGEND R W Read Write R Read only W1CP Write 1 in privilege mode to clear the bit n value after reset Ta...

Page 1163: ...rite R Read only W1CP Write 1 in privilege mode to clear the bit n value after reset Table 24 30 BER Interrupt Flag Register HTU BERINTFL Field Descriptions Bit Field Value Description 31 16 Reserved...

Page 1164: ...accesses an address smaller than STARTADDRESS1 and the MPCS bit REG01ENA register is configured accordingly The address is 32 bit aligned so the 2 LSBs are not significant and will always read 0 24 4...

Page 1165: ...of DCP0 2h CP A of DCP1 3h CP B of DCP1 4h CP A of DCP2 5h CP B of DCP2 6h CP A of DCP3 7h CP B of DCP3 8h CP A of DCP4 9h CP B of DCP4 Ah CP A of DCP5 Bh CP B of DCP5 Ch CP A of DCP6 Dh CP B of DCP6...

Page 1166: ...set then the application code execution is stopped This register can only be programmed during debug mode This register and all other bits of the DCTRL and WMR registers are reset by the test reset nT...

Page 1167: ...Class Subtype Number R Module Revision Number LEGEND R Read only n value after reset Table 24 36 Module Identification Register HTU ID Field Descriptions Bit Field Value Description 31 24 Reserved 0...

Page 1168: ...then the DCP x will automatically be disabled in the CPENA register If a frame is active on DCP x during this read access then in addition the element counter of DCP x is cleared and all new element t...

Page 1169: ...ity error and parity checking is enabled 0 No fault is detected 1 Fault is detected Note Once PEFT is set a read access to the lower 16 bits or to the complete 32 bit HTUPAR register will clear the PE...

Page 1170: ...irst memory protection error when only one memory protection region is used This number is not updated for multiple access violations until it is read by the CPU During debug mode CPNUM0 is frozen eve...

Page 1171: ...ess is allowed but write access will be signaled 1 Any access performed by the HTU is forbidden and will be signaled 3 REG01ENA Region Enable 01 This bit needs to be set when working with two memory m...

Page 1172: ...ined by the MP0S and MP0E registers is not enabled This means the HTU can access any implemented memory space 1 The protection outside the memory region defined by the MP0S and MP0E registers is enabl...

Page 1173: ...the HTU accesses an address smaller than STARTADDRESS0 and the MPCS register is configured accordingly The address is 32 bit aligned so the 2 LSBs are not significant and will always read 0 24 4 28 Me...

Page 1174: ...DCP0 ITCOUNT Initial Transfer Count Register Section 24 5 4 10h HTU DCP1 IFADDRA Initial Full Address A Register Section 24 5 1 14h HTU DCP1 IFADDRB Initial Full Address B Register Section 24 5 2 18h...

Page 1175: ...iption 31 0 IFADDRA Initial Address of Buffer A in main memory Initial byte address of buffer A placed in the main memory address range Bits 0 and 1 are ignored by the logic due to 32 bit alignment 24...

Page 1176: ...rred 21 ADDMH Addressing Mode N2HET Address This bit determines the N2HET address index from one to the next element of a frame 0 Increment by 16 bytes Examples If the initial N2HET address points to...

Page 1177: ...required for the actual N2HET RAM size If the N2HET address exceeds the actual N2HET RAM size the unused MSB bits of the address will be ignored and the address rolls over to the start of the N2HET R...

Page 1178: ...re to find out the recently transferred element in the frozen buffer while the address of the active buffer increments Note A frame can be automatically stopped if any of the events listed in Conditio...

Page 1179: ...software to find out the recently transferred element in the frozen buffer while the address of the active buffer increments Note A frame can be automatically stopped if any of the events listed in Co...

Page 1180: ...48 Current Frame Count Register HTU CFCOUNT 31 24 23 16 Reserved CFTCTA R 0 R WP X 15 8 7 0 Reserved CFTCTB R 0 R WP X LEGEND R W Read Write R Read only WP Write in privilege mode only n value after r...

Page 1181: ...d is determined by the time of the interrupt determined by the frequency of the N2HET transfer requests 24 6 2 Software Example Sequence Assuming Circular Mode for Both CP A and B The example assumes...

Page 1182: ...After reading the CPU does not need to clear the frozen buffer B After some time the CPU intends to read buffer A A1 see above NOTE The buffer full interrupt doesn t need to be enabled The BFINTFL fl...

Page 1183: ...he general purpose input output GIO module The GIO module provides the family of devices with input output I O capability The I O pins are bidirectional and bit programmable The GIO module also suppor...

Page 1184: ...on The GIO module also supports generation of interrupts whenever a rising edge or falling edge or any toggle is detected on up to 32 of these GIO terminals Refer to the device datasheet for identifyi...

Page 1185: ...ding bits in to GIOPSL to 1 Read corresponding bits in GIODIN getting input value Write 1 to corresponding bits inGIODSET Write 1 to corresponding bits in GIODCLR www ti com Quick Start Guide 1185 SPN...

Page 1186: ...l High level Write 1 to corresponding bits in to enable interrupt GIOENASET Write 0xFF to clean the GIO interrupt flag register GIOFLG Enable Peripherals by setting PENA bit in Clock Control Register...

Page 1187: ...OUT Configures the logic level to be output on GIO terminal s configured as outputs A low value 0 written to the data output register forces the pin to a low output voltage V OL or lower A high value...

Page 1188: ...n the selected GIO pin s that is are used to generate interrupt s rising falling both Rising or falling edge can be selected via the GIOPOL register If interrupt is required to be generated on both ri...

Page 1189: ...pt handling 1 High level level A interrupt handling 1 To VIM To VIM www ti com Functional Description of GIO Module 1189 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instrume...

Page 1190: ...ring the flags During emulation mode External interrupts are not captured because the VIM is unable to service interrupts Any register can be read without affecting the state of the system A write to...

Page 1191: ...O Interrupt Enable Clear Register Section 25 5 4 2 18h GIOLVLSET GIO Interrupt Priority Set Register Section 25 5 5 1 1Ch GIOLVLCLR GIO Interrupt Priority Clear Register Section 25 5 5 2 20h GIOFLG GI...

Page 1192: ...any other register of the GIO module Figure 25 5 and Table 25 2 describe this register Figure 25 5 GIO Global Control Register GIOGCR0 offset 00h 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LE...

Page 1193: ...NTDET 3 Interrupt detection select for pins GIOD 7 0 0 The flag sets on either a falling or a rising edge on the corresponding pin depending on the polarity setup in the polarity register GIOPOL 1 The...

Page 1194: ...ponding pin Low power mode GIO module clocks off 0 The interrupt is triggered on the low level 1 The interrupt is triggered on the high level 23 16 GIOPOL 2 Interrupt polarity select for pins GIOC 7 0...

Page 1195: ...rupt Enable Set Register GIOENASET offset 10h 31 24 23 16 GIOENASET 3 GIOENASET 2 R W 0 R W 0 15 8 7 0 GIOENASET 1 GIOENASET 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 25 5 GIO Inte...

Page 1196: ...lue Description 31 24 GIOENACLR 3 Interrupt disable for pins GIOD 7 0 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read The interrupt is enabled Write Disables the in...

Page 1197: ...1 16 GIOLVLSET 3 GIOLVLSET 2 R W 0 R W 0 15 8 7 0 GIOLVLSET 1 GIOLVLSET 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 25 7 GIO Interrupt Priority Register GIOLVLSET Field Descriptions...

Page 1198: ...ld Value Description 7 0 GIOLVLSET 0 GIO high priority interrupt for pins GIOA 7 0 0 Read The interrupt is a low level interrupt The low level interrupts are recorded to GIOOFF2 and GIOEMU2 Write Writ...

Page 1199: ...GIOEMU1 Write Sets the interrupt as a low level interrupt The low level interrupts are recorded to GIOOFF2 and GIOEMU2 23 16 GIOLVLCLR 2 GIO low priority interrupt for pins GIOC 7 0 0 Read The interr...

Page 1200: ...in the appropriate offset register 23 16 GIOFLG 2 GIO flag for pins GIOC 7 0 0 Read A transition has not occurred since the last clear Write Writing a 0 to this bit has no effect 1 Read The selected t...

Page 1201: ...y pending interrupt The application can choose to service all GIO interrupts from the same service routine by continuing to read the GIOOFF1 register until it reads zeros Figure 25 13 GIO Offset 1 Reg...

Page 1202: ...rity pending interrupt The application can choose to service all GIO interrupts from the same service routine by continuing to read the GIOOFF1 register until it reads zeros Figure 25 14 GIO Offset 2...

Page 1203: ...r GIOEMU1 offset 2Ch 31 16 Reserved R 0 15 6 5 0 Reserved GIOEMU1 R 0 R 0 LEGEND R Read only n value after reset Table 25 12 GIO Emulation 1 Register GIOEMU1 Field Descriptions Bit Field Value Descrip...

Page 1204: ...ister GIOEMU2 offset 30h 31 16 Reserved R 0 15 6 5 0 Reserved GIOEMU2 R 0 R 0 LEGEND R Read only n value after reset Table 25 13 GIO Emulation 2 Register GIOEMU2 Field Descriptions Bit Field Value Des...

Page 1205: ...1 8 Reserved 0 Reads return 0 Writes have no effect 7 0 GIODIR n GIO data direction of port n pins 7 0 0 The GIO pin is an input Note If the pin direction is set as an input the output buffer is trist...

Page 1206: ...o logic low 0 1 The pin is driven to logic high 1 Note Output is in high impedance state if the GIOPDRx bit 1 and GIODOUTx bit 1 Note GIO pin is placed in output mode by setting the GIODIRx bit to 1 2...

Page 1207: ...1 Write The corresponding GIO pin is driven to logic low 0 Note The current logic state of the GIODOUT bit will also be displayed by this bit Note GIO pin is placed in output mode by setting the GIODI...

Page 1208: ...e GIO pin configured as an input pin 0 The pull functionality is enabled 1 The pull functionality is disabled Note The GIO pin is placed in input mode by clearing the GIODIRx bit to 0 25 5 18 GIO Pull...

Page 1209: ...isabling pull control 5 GIOPSL 0 for pull down functionality 1 for pull up functionality 6 If open drain is enabled output buffer will be disabled if a high level 1 is being output Table 25 22 Output...

Page 1210: ...orporated FlexRay Module Chapter 26 SPNU563A March 2018 FlexRay Module This chapter provides the specification for TI s FlexRay module and its features from the application programmer s point of view...

Page 1211: ...ation v2 1 Rev A Data rates of up to 10 Mbit s on each channel Up to 128 message buffers 8 Kbyte of message RAM for storage of for example 128 message buffers with maximum of 48 byte data section or u...

Page 1212: ...handler then transfers the data from the input buffer to the selected message buffer in the message RAM Output Buffer OBF For read access to a message buffer configured in the message RAM the message...

Page 1213: ...t buffer RAM Message handler Global Time Unit System universal control Frame and symbol processing Network management Interrupt control Global time unit GTU The GTU performs the following functions Ge...

Page 1214: ...ch time capturing 80 MHz Clock Signal NOTE VCLKA2 is used to provide the 80 MHz clock to the FlexRay Module The second PLL Clock Source 6 in the microcontroller is typically used as source for VCLKA2...

Page 1215: ...BF are 8 16 and 32 bit accessible For transfers using the Transfer Unit State Machine only 4 32 bit data packages 4 word bursts are supported The Interface Arbiter controls the access to the IBF and O...

Page 1216: ...it State Machine Interface Arbiter Transfer Configuration RAM TCR Handler Message FlexRay FlexRay Input Buffer FlexRay Output Buffer IBF OBF Module Operation www ti com 1216 SPNU563A March 2018 Submit...

Page 1217: ...n Figure 26 4 shows the principle of the Transfer Unit operation Each FlexRay message buffer of the FlexRay message buffer RAM has one Transfer Configuration RAM TCR entry assigned to it that is messa...

Page 1218: ...Configuration RAM TCR 4 word burst by 4 word burst transfer of message buffer to System Memory SM or to Communication Controller CC Reset bit in TTSM or TTCC which corresponds to the transferred messa...

Page 1219: ...lted effectively stopping the Transfer Unit transfer sequence after completion of the current 4 word burst transfer cycle After releasing from halt state the Transfer Unit resumes exactly where it was...

Page 1220: ...Transfer Configuration RAM TCR Table 26 2 FlexRay Transfer Unit Event Trigger Conditions Event on Channel A Event on Channel B Frame belonging to static segment or first slot of dynamic segment Frame...

Page 1221: ...umber of transferred payload words is derived from the Payload Length Configured PLC information configured in the Write Header Section 2 WRHS2 register As only 4 word bursts are supported for the Tra...

Page 1222: ...to Communication Controller LTBCC Last Transferred Buffer to System Memory LTBSM Transfer to System Memory Occurred 1 2 3 4 TSMO1 4 Transfer to Communication Controller Occurred 1 2 3 4 TCCO1 4 Trans...

Page 1223: ...Address TBA register Each entry of the TCR holds a 14 bit offset value TSO The TSO offset will be added to the content of the TBA register The TBA register holds the 32bit base address pointer to a l...

Page 1224: ...tion Controller should be set This would trigger the transfer to the FlexRay bus If a data and header section transfer is selected the number of 32 bit words to be transferred is read from the Payload...

Page 1225: ...e a data word is read from the TCR RAM If an ECC error is detected the PE error flag is set in the Transfer Error Interrupt Flag TEIF register The detection of an ECC single bit error will be indicate...

Page 1226: ...following features Time slots of fixed length optionally protected by bus guardian Start of frame transmission at action point of the corresponding static slot Payload length same for all frames on bo...

Page 1227: ...h 1MT The static segment length is configured by GTUC7 SSL and GTUC7 NSS The dynamic segment length is configured by GTUC8 MSL and GTUC8 NMS The dynamic segment offset is ActionPointOffset MinislotAct...

Page 1228: ...ick T typically 25ns T basic unit of time measurement in a communication controller clock correction is done in units of Ts Cycle counter macrotick counter nodes local view of the global time 26 2 4 3...

Page 1229: ...d integer External offset rate correction value is added to calculated offset rate correction value Aggregated offset rate correction term external internal is not checked against configured limits 26...

Page 1230: ...evented if SUCC1 HCSE is not set 26 2 5 2 Passive to Active Counter The passive to active counter controls the transition of the POC from NORMAL_PASSIVE to NORMAL_ACTIVE state SUCC1 SUCC1 PTA 4 0 defi...

Page 1231: ...1231 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated FlexRay Module 26 2 6 Communication Controller States 26 2 6 1 Communication Controller State Diag...

Page 1232: ...aximum without clock correction fatal limit configured by SUCC3 WCF 3 0 AND bit SUCC1 HCSE set to 1 OR command HALT SUCC1 CMD 3 0 0110 NORMAL_ACTIVE HALT 15 Clock Correction Failed counter reached max...

Page 1233: ...receive message buffer may only be configured to receive on one channel Received frames are stored into message buffers according to frame ID and receive channel Null frames are handled like data fram...

Page 1234: ...ttern on each of its available channels separately The communication controller needs to recognize the wakeup pattern only during wakeup and startup phase Wakeup may be performed on only one channel a...

Page 1235: ...LISTEN WAKEUP_SEND 4 Complete non aborted transmission of wakeup pattern WAKEUP_SEND WAKEUP_STANDBY 5 Collision detected WAKEUP_SEND WAKEUP_DETECT 6 Wakeup timer expired OR WUP detected on wakeup chan...

Page 1236: ...host must coordinate the wakeup of the two channels and must decide whether or not to wake a specific channel The sending of the wakeup pattern is initiated by the host The wakeup pattern is detected...

Page 1237: ...g description is intended to help configuring startup for the FlexRay module A detailed description of the startup procedure can be found in the FlexRay protocol specification v2 1 Rev A Any node ente...

Page 1238: ...may start integration before the coldstart nodes have finished their startup It will not finish its startup until at least two coldstart nodes have finished their startup Both non coldstart nodes and...

Page 1239: ...P ABORT STARTUP ABORT STARTUP COLDSTART GAP STARTUP PREPARE INTEGRATION CONSISTENCY CHECK INITIALIZE SCHEDULE NORMAL ACTIVE COLDSTART CONSISTENCY CHECK COLDSTART JOIN ABORT STARTUP ABORT STARTUP ABORT...

Page 1240: ...tup timeout expires neither an overflow nor a cyclic restart of the timer is performed The timer status is kept for further processing by the startup state machine 26 2 6 7 2 2 Startup Noise Timeout A...

Page 1241: ...lid startup frame and derive a schedule from this the INTEGRATION_COLDSTART_CHECK state is entered In INTEGRATION_COLDSTART_CHECK state it is assured that the clock correction can be performed correct...

Page 1242: ...CMD 3 0 0110 HALT command at the end of the current cycle HALT state by writing SUCC1 CMD 3 0 0111 FREEZE command immediately HALT state due to change of the error state from ACTIVE to COMM_HALT NORMA...

Page 1243: ...Preamble Indicator PPI bit set Only a static frame may be configured to hold NM information The communication controller updates the NM vector at the end of each cycle The length of the NM vector can...

Page 1244: ...lements of the cycle set is matched The cycle set is defined by the cycle code field in the header section 1 of each message buffer If message buffer 0 or 1 is configured to hold the startup sync fram...

Page 1245: ...and cycle counter filtering criteria are also met Only in static segment a transmit buffer may be set up for transmission on both channels CHA and CHB set Valid received frames are stored if they are...

Page 1246: ...ller channels Static segment channel A or channel B channel A and channel B Dynamic segment channel A or channel B Message buffer 0 or 1 is dedicated to hold the startup frame the sync frame or the de...

Page 1247: ...hrough WRHS1 WRHS2 and WRHS3 Write the data section of the transmit buffer through WRDSn Transfer the configuration and message data from Input Buffer to the Message RAM by writing the number of the t...

Page 1248: ...guration from input buffer to the message RAM by writing the number of the target message buffer to the Input Buffer Command Request IBCR register Once these steps are performed the message buffer fun...

Page 1249: ...th the FIFO The PUT Index register PIDX is an index to the next available location in the FIFO When a new message has been received it is written into the message buffer addressed by the PIDX register...

Page 1250: ...for acceptance filtering is taken from the FIFO rejection filter and the FIFO rejection filter mask With the exception of DP and PLC the values configured in the header sections of the message buffer...

Page 1251: ...eted Therefore it may happen that a reconfigured message buffer is not transmitted updated from a received frame in the cycle where it was reconfigured The Message RAM is scanned according to Table 26...

Page 1252: ...ource message buffer to be accessed to the input or output buffer command request register IBCR OBCR The input output buffer command mask registers can be used to write read header and data section of...

Page 1253: ...the input buffer command request register is set to 1 The message handler then starts to transfer the contents of IBF shadow to the message buffer in the message RAM selected by IBCR IBRS 6 0 While t...

Page 1254: ...shadow ongoing or finished 17 r LDSS Load Data Section shadow ongoing or finished 16 r LHSS Load Header Section shadow ongoing or finished 2 r w STXRH Set Transmission Request Host 1 r w LDSH Load Da...

Page 1255: ...OBCR REQ from the output buffer command request register Writing bit OBCR REQ in the output buffer command request register to 1 copies bits OBCM RHSS OBCM RDSS from the output buffer command mask reg...

Page 1256: ...write accesses to OBCR REQ and OBCR VIEW are necessary Wait until OBCR OBSYS is reset Write Output Buffer Command Mask OBCM RHSS OBCM RDSS Request transfer of message buffer to OBF Shadow by writing...

Page 1257: ...RAM The two transient buffer RAMs TBF A B are used to buffer the data for transfer between the two FlexRay channel protocol controllers and the message RAM Each transient buffer RAM is built up as a d...

Page 1258: ...AM Transient Buffer RAM Channel A TBF A Transient Buffer RAM Channel B TBF B Input Buffer IBF Input Buffer Shadow IBFS Output Buffer OBF Output Buffer Shadow OBFS Transfer Configuration RAM TCR All RA...

Page 1259: ...data partition may not occupy more than 2048 x 32 bit words 26 2 13 1 1 Header Partition The elements used for configuration of a message buffer as well as the current message buffer status are store...

Page 1260: ...Documentation Feedback Copyright 2018 Texas Instruments Incorporated FlexRay Module Payload length received PLR 6 0 receive cycle count RCC 5 0 Received on Channel Indication RCI Startup Frame Indicat...

Page 1261: ...SYN Sync Frame Indicator NFI Null Frame Indicator PPI Payload Preamble Indicator RES REServed bit Message Buffer Status MBS Word 3 Read access through MBS updated by the communication controller at th...

Page 1262: ...ber of 2 byte words the remaining 16 bits in the last 32 bit word are unused see Figure 26 25 Figure 26 25 Example Structure of Data Partition in Message RAM Bit Word 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2...

Page 1263: ...C lock bits PEL 3 0 ECC protection can not be switched off completely For the TCR of the Transfer Unit actually the ECC multi bit error generation will be switched on and off by the ECC lock bits the...

Page 1264: ...on key SBE_EVT_EN in ECC_CTRL is enabled When single bit error correction is turned off the ECC algorithm will detect up to 3 bits in error in a word For ECC multi bit errors the faulty message buffer...

Page 1265: ...x 5 x x x x x x x x x x x x x x x x 4 x x x x x x x x x x x x x x x x 3 x x x x x x x x x x x x x x x x 2 x x x x x x x x x x x x x x x x 1 x x x x x x x x x x x x x x x x 0 ECC Error Bits for Syndrom...

Page 1266: ...t for the corresponding message buffer is not set no transfer to the FlexRay bus b Transfer of data section only and ECC multi bit error occurs when reading header section of the corresponding message...

Page 1267: ...RAM 1 2 When an ECC multi bit error occurs during the Message Handler reads a frame with network management information PPI 1 from the transient buffer RAM 1 2 the corresponding network management vec...

Page 1268: ...n of corresponding message buffer from message RAM SBESTAT SMR bit is set SBESTAT FMBD bit is set to indicate that SBESTAT FMB 6 0 points to a faulty message buffer SBESTAT FMB 6 0 indicates the numbe...

Page 1269: ...immediately preceded by the unlock sequence normally used to leave CONFIG state For that single transfer the corresponding message buffer header is unlocked regardless whether it belongs to the FIFO...

Page 1270: ...gs TEIF Error Interrupt Mask TEIRES R Uncorrectable TCR error Memory Protection Violation TU_UCT_err to ESM TU_MPV_err to ESM VBUS read VBUS write Transfer Buffer 128 TCR Single Bit Error Status TSBES...

Page 1271: ...t State Machine sets it at the same time the flag remains set 26 2 14 1 4 Nonmaskable Error Indication Memory protection violation and uncorrectable TCR error have their own nonmaskable error lines wh...

Page 1272: ...r occurs are two independent tasks Independent of an interrupt being enabled the corresponding status is tracked and indicated by the Communication Controller The host has access to the current status...

Page 1273: ...hannel A TABA Transmission Across Boundary Channel A EDB Error Detected on Channel B LTVB Latest Transmit Violation Channel B TABB Transmission Across Boundary Channel B SIR WST Wakeup Status CAS Coll...

Page 1274: ...maximum value of 3 The find sequence is executed each 8 slots slot 8 16 24 32 40 It has to be finished until the next find sequence is requested The duration of a Transient Buffer RAM TBF transfer to...

Page 1275: ...l SUCC3 WCF 3 0 gNetworkManagementVectorLength NEMC NML 3 0 gdTSSTransmitter PRTC1 TSST 3 0 gdCASRxLowMax PRTC1 CASM 6 0 gdSampleClockPeriod PRTC1 BRP 1 0 pSamplesPerMicrotick PRTC1 BRP 1 0 gdWakeupSy...

Page 1276: ...inislotActionPointOffset GTUC9 MAPO 4 0 gdDynamicSlotIdlePhase GTUC9 DSI 1 0 pOffsetCorrectionOut GTUC10 MOC 13 0 pRateCorrectionOut GTUC10 MRC 10 0 pExternOffsetCorrection GTUC11 EOC 2 0 pExternRateC...

Page 1277: ...d 1 Section 26 3 1 12 044h TSMO2 Transfer to System Memory Occurred 2 Section 26 3 1 12 048h TSMO3 Transfer to System Memory Occurred 3 Section 26 3 1 12 04Ch TSMO4 Transfer to System Memory Occurred...

Page 1278: ...22 0F0h CESMS3 Clear on Event to System Memory Set 3 Section 26 3 1 22 0F4h CESMR3 Clear on Event to System Memory Reset 3 Section 26 3 1 22 0F8h CESMS4 Clear on Event to System Memory Set 4 Section...

Page 1279: ...n value after reset Table 26 19 Global Static Number 0 GSN0 Field Descriptions Bit Field Value Description 31 16 Data_A 0 FFFFh Data_A 15 0 Data_B 0 FFFFh Complement of Data_A 26 3 1 2 Global Static N...

Page 1280: ...10h 31 30 29 28 27 26 25 24 ENDVBM ENDVBS ENDR ENDH ENDP R S 0 R S 0 R S 0 R S 0 R S 0 23 22 21 20 19 16 Reserved PRIO Reserved PEL R 0 R S 0 R 0 R S 5h 15 14 13 12 11 9 8 Reserved CETESM CTTCC CTTSM...

Page 1281: ...ed to CDABh 3h Remapped to DCBAh 27 26 ENDH Endianness Correction for Header 0 Remapped to ABCDh 1h Remapped to BADCh 2h Remapped to CDABh 3h Remapped to DCBAh 25 24 ENDP Endianness Correction for Pay...

Page 1282: ...ine Enable Enable error interrupt line 0 TU_Int1 is disabled 1 TU_Int1 is enabled 3 2 Reserved 0 Reads return 0 Writes have no effect 1 TUH Transfer Unit Halted When halted the Transfer Unit State Mac...

Page 1283: ...in debug mode in combination with a debugger In Normal Operation Mode the value of TSMS is always read as 0 1h IDLE state Transfer Trigger to System Memory 2h Start state TTSM_START 3h Output Buffer...

Page 1284: ...ller Figure 26 37 Last Transferred Buffer to Communication Controller LTBCC offset_TU 1Ch 31 7 6 0 Reserved BN R 0 R 0 LEGEND R Read only n value after reset Table 26 23 Last Transferred Buffer to Com...

Page 1285: ...ase Address TBA Field Descriptions Bit Field Description 31 0 TBA Transfer Base Address 32 bit base pointer 2 LSB are not significant 32 bit accesses only and will always be 0 26 3 1 8 Next Transfer B...

Page 1286: ...o be use for mirror transactions Further details about the transfer mirror mechanism can be found in Section 26 2 1 1 1 7 Figure 26 41 Base Address of Mirrored Status BAMS offset_TU 2Ch 31 16 BAMS R W...

Page 1287: ...address of the memory area which allows read and write accesses for the Transfer Unit State Machine 32 bit base pointer 2 LSB are not significant 32 bit accesses only will always be 0 26 3 1 11 End A...

Page 1288: ...m Memory Occurred 1 TSMO1 offset_TU 40h 31 16 TSMO1 31 16 R W1C 0 15 0 TSMO1 15 0 R W1C 0 LEGEND R W Read Write W1C Write 1 to clear n value after reset Figure 26 45 Transfer to System Memory Occurred...

Page 1289: ...stem Memory Occurred TSMOn Field Descriptions Bit Field Value Description 31 0 TSMO 1 4 n Transfer to System Memory Occurred Register The register bits correspond to message buffers 0 to 127 Each bit...

Page 1290: ...Controller Occurred 1 TCCO1 offset_TU 50h 31 16 TCCO1 31 16 R W1C 0 15 0 TCCO1 15 0 R W1C 0 LEGEND R W Read Write W1C Write 1 to clear n value after reset Figure 26 49 Transfer to Communication Contr...

Page 1291: ...Controller Occurred TCCOn Field Descriptions Bit Field Value Description 31 0 TCCO 1 4 n Transfer to Communication Controller Occurred Register The register bits correspond to message buffers 0 to 127...

Page 1292: ...erved TDIR OFF R 0 R 0 R 0 LEGEND R Read only n value after reset Table 26 32 Transfer Occurred Offset TOOFF Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reads return 0 Writes have n...

Page 1293: ...reading it Figure 26 53 TCR Single Bit Error Status TSBESTAT offset_TU 6Ch 31 30 16 SE Reserved R 0 R 0 15 9 8 0 Reserved ADR R 0 RC U LEGEND R Read only RC Clear on read U value is undefined n value...

Page 1294: ...ECC Error Address register NOTE An ECC multi bit error can only be indicated by the PE bit of TEIF register when PEADR is cleared Since the contents of PEADR is undefined after reset it is recommende...

Page 1295: ...ield Descriptions Bit Field Value Description 31 18 Reserved 0 Reads return 0 Writes have no effect 17 MPV Memory Protection Violation 0 No MPV occurred 1 MPV occurred 16 PE ECC Error The flag signals...

Page 1296: ...an 000 indicates a VBUS read error The information of the specific VBUS fault is for debug reasons only and is not relevant for normal usage 3 2 Reserved 0 Reads return 0 Writes have no effect 1 TNR T...

Page 1297: ...offset_TU 78h 31 16 Reserved R 0 15 11 10 8 7 6 4 3 2 1 0 Reserved RSTATE RSVD WSTATE Reserved TNRE FACE R 0 R WS 0 R 0 R WS 0 R 0 R WS 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after...

Page 1298: ...Interrupt generation on VBUS read transfer error is disabled 7h Interrupt generation on VBUS read transfer error is enabled Note Any value different from 111 does not assure the interrupt error gener...

Page 1299: ...W Read Write R Read only S Set n value after reset Table 26 38 Trigger Transfer to System Memory Set 1 TTSMS1 Field Descriptions Bit Field Value Description 31 0 TTSMS1 n Trigger Transfer to System M...

Page 1300: ...espond to message buffers 32 to 63 Each bit of the register controls the message buffer transfer to the system memory in the following manner note that only the least significant bit of all four combi...

Page 1301: ...espond to message buffers 64 to 95 Each bit of the register controls the message buffer transfer to the system memory in the following manner note that only the least significant bit of all four combi...

Page 1302: ...respond to message buffers 96 to 127 Each bit of the register controls the message buffer transfer to the system memory in the following manner note that only the least significant bit of all four com...

Page 1303: ...16 R WS 0 15 0 TTCCS1 15 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after reset Table 26 46 Trigger Transfer to Communication Controller Set 1 TTCCS1 Field Descriptions Bit Field Value...

Page 1304: ...nication Controller Set 2 The register bits 0 to 31 correspond to message buffers 32 to 63 Each bit of the register controls the message buffer transfer to the communication controller in the followin...

Page 1305: ...nication Controller Set 3 The register bits 0 to 31 correspond to message buffers 64 to 95 Each bit of the register controls the message buffer transfer to the communication controller in the followin...

Page 1306: ...unication Controller Set 4 The register bits 0 to 31 correspond to message buffers 96 to 127 Each bit of the register controls the message buffer transfer to the communication controller in the follow...

Page 1307: ...R WS 0 15 0 ETESMS1 15 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after reset Table 26 54 Enable Transfer on Event to System Memory Set 1 Field Descriptions Bit Field Value Description...

Page 1308: ...fer on Event to System Memory Set 2 The register bits 0 to 31 correspond to message buffers 32 to 63 Each bit of the register enables a message buffer transfer on event to the system memory 0 Transfer...

Page 1309: ...fer on Event to System Memory Set 3 The register bits 0 to 31 correspond to message buffers 64 to 95 Each bit of the register enables a message buffer transfer on event to the system memory 0 Transfer...

Page 1310: ...sfer on Event to System Memory Set 4 The register bits 0 to 31 correspond to message buffers 96 to 127 Each bit of the register enables a message buffer transfer on event to the system memory 0 Transf...

Page 1311: ...SMS1 31 16 R WS 0 15 0 CESMS1 15 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after reset Table 26 62 Clear on Event to System Memory Set 1 CESMS1 Field Descriptions Bit Field Value Descri...

Page 1312: ...MS2 n Clear on Event to System Memory Set 2 The register bits 0 to 31 correspond to message buffers 32 to 63 Each bit of the register enables an automatic clear of the corresponding ETESM2 bit after a...

Page 1313: ...MS3 n Clear on Event to System Memory Set 3 The register bits 0 to 31 correspond to message buffers 64 to 95 Each bit of the register enables an automatic clear of the corresponding ETESM3 bit after a...

Page 1314: ...SMS4 n Clear on Event to System Memory Set 4 The register bits 0 to 31 correspond to message buffers 96 to 127 Each bit of the register enables an automatic clear of the corresponding ETESM4 bit after...

Page 1315: ...16 R WS 0 15 0 TSMIES1 15 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after reset Table 26 70 Transfer to System Memory Interrupt Enable Set 1 TSMIES1 Field Descriptions Bit Field Value D...

Page 1316: ...er to System Memory Interrupt Enable Set 2 The register bits 0 to 31 correspond to message buffers 32 to 63 Each bit of the register enables a potential interrupt which occurs if the corresponding TSM...

Page 1317: ...er to System Memory Interrupt Enable Set 3 The register bits 0 to 31 correspond to message buffers 64 to 95 Each bit of the register enables a potential interrupt which occurs if the corresponding TSM...

Page 1318: ...fer to System Memory Interrupt Enable Set 4 The register bits 0 to 31 correspond to message buffers 96 to 127 Each bit of the register enables a potential interrupt which occurs if the corresponding T...

Page 1319: ...WS 0 15 0 TCCIES1 15 0 R WS 0 LEGEND R W Read Write R Read only S Set n value after reset Table 26 78 Transfer to Communication Controller Interrupt Enable Set 1 TCCIES1 Field Descriptions Bit Field V...

Page 1320: ...nication Controller Interrupt Enable Set 2 The register bits 0 to 31 correspond to message buffers 32 to 63 Each bit of the register enables a potential interrupt which occurs if the corresponding TCC...

Page 1321: ...nication Controller Interrupt Enable Set 3 The register bits 0 to 31 correspond to message buffers 64 to 95 Each bit of the register enables a potential interrupt which occurs if the corresponding TCC...

Page 1322: ...unication Controller Interrupt Enable Set 4 The register bits 0 to 31 correspond to message buffers 96 to 127 Each bit of the register enables a potential interrupt which occurs if the corresponding T...

Page 1323: ...o the communication controller 17 THTSM Transfer Header to System Memory 0 Transfer Unit State Machine will not transfer buffer header to system memory 1 Transfer Unit State Machine will transfer buff...

Page 1324: ...nd can be read or written The corresponding TCR entry can be found by subtracting 0x200 from the TCR offset Figure 26 107 ECC Information in TCR ECC Test Mode offset_TU_RAM 200h 3FCh 31 16 Reserved R...

Page 1325: ...segment Static Dynamic buffers Transmit receive buffers assigned to static or dynamic segment FIFO Receive FIFO The message buffer separation configuration can be changed in DEFAULT_CONFIG or CONFIG s...

Page 1326: ...p Watch Register 2 Section 26 3 2 2 11 Communication Controller Control Registers 80h SUCC1 SUC Configuration Register 1 Section 26 3 2 3 1 84h SUCC2 SUC Configuration Register 2 Section 26 3 2 3 2 88...

Page 1327: ...ection 26 3 2 6 5 32Ch TXRQ4 Transmission Request Register 4 Section 26 3 2 6 5 330h NDAT1 New Data Register 1 Section 26 3 2 6 6 334h NDAT2 New Data Register 2 Section 26 3 2 6 6 338h NDAT3 New Data...

Page 1328: ...Indication 5h ECC single bit error indication is disabled On ECC single bit error detection when reading from message RAM transient buffer RAMs input buffer RAMs and output buffer RAMs the single bit...

Page 1329: ...r reset Table 26 90 ECC Diagnostic Status Register ECCDSTAT Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reads return 0 Writes have no effect 23 DEFH ECC Double Bit Error Flag for F...

Page 1330: ...enabled 5 SEFF ECC Single Bit Error Flag for Transient Buffer B RAM 0 No ECC single bit error is detected 1 ECC single bit error is detected and diagnostic mode is enabled 4 SEFE ECC Single Bit Error...

Page 1331: ...in RDECC bitfield Writing to a certain ECC location copies the contents of WRECC bitfield to the corresponding ECC location Figure 26 111 and Table 26 91 illustrate this register NOTE For FTU RAM a se...

Page 1332: ...er reset Table 26 92 Single Bit Error Status Register SBESTAT Field Descriptions Bit Field Value Description 31 SBE ECC Single Bit Error The flag signals an ECC single bit error to the host The flag i...

Page 1333: ...single bit error 1 ECC single bit error occurred when reading transient buffer RAM A 2 SMR ECC single bit error in message RAM 0 No ECC single bit error 1 ECC single bit error occurred when reading me...

Page 1334: ...be combined with each other or with FlexRay protocol functions NOTE The FlexRay module should be kept in CONFIG state while RAM Test Mode TMC 01 is enabled The test mode features are intended for har...

Page 1335: ...odes regarding CAS MTS symbols concern only the monitored bit pattern irrelevant whether those bit patterns occurred in the symbol window or elsewhere 23 22 Reserved 0 Reads return 0 Writes have no ef...

Page 1336: ...ost interface command vector CMD in the SUC configuration register 1 controller host interface command ATM while the communication controller is in CONFIG state and bit WRTEN in the test register 1 is...

Page 1337: ...at this transmitted message like a received message perform an acceptance filtering on frame ID and receive channel and store the message into the message RAM assuming the message passed the acceptanc...

Page 1338: ...e is enabled this bit is always read as 0 14 WRPB 0 1 When ECC mode is enabled this bit has no effect 13 7 Reserved 0 Reads return 0 Writes have no effect 6 4 SSEL Segment select To enable access to t...

Page 1339: ...Figure 26 115 For external RAM access in RAM test mode the selected RAM block is mapped to the address range offset_CC 400h to 7FFh which is the address space for the input and output buffer register...

Page 1340: ...sequence If this write sequence is interrupted by other write accesses bit WRTEN is not set to 1 and the sequence has to be repeated First write LCK TMK 75h 0b0111 0101 Second write LCK TMK 8Ah 0b1000...

Page 1341: ...B 25 LTVB Latest transmit violation channel B The flag signals a latest transmit violation on channel B to the host 0 No latest transmit violation is detected on channel B 1 Latest transmit violation...

Page 1342: ...to empty FIFO occurred 7 RFO Receive FIFO overrun This flag is set by the communication controller when a receive FIFO overrun was detected The flag is cleared by the next FIFO read access of the hos...

Page 1343: ...ng while one of the bits is set A flag is cleared by writing a 1 to the corresponding bit position Writing a 0 has no effect on the flag A hardware reset will also clear the register Figure 26 118 and...

Page 1344: ...nerate a stop watch event 0 No stop watch event 1 Stop watch event occurred 11 TOBC Transfer output buffer completed This flag is set whenever a transfer from the message RAM to the output buffer has...

Page 1345: ...buffer and if bit MBI of that message buffer is set to 1 0 No data section has been updated 1 At least one data section has been updated 3 TXI Transmit interrupt This flag is set by the communication...

Page 1346: ...line 0 Interrupt is assigned to interrupt line CC_int0 1 Interrupt is assigned to interrupt line CC_int1 24 EDBL Error detected on channel B interrupt line 0 Interrupt is assigned to interrupt line CC...

Page 1347: ...ssigned to interrupt line CC_int0 1 Interrupt is assigned to interrupt line CC_int1 4 CCFL Clock correction failure interrupt line 0 Interrupt is assigned to interrupt line CC_int0 1 Interrupt is assi...

Page 1348: ...Wakeup pattern channel B interrupt line 0 Interrupt is assigned to interrupt line CC_int0 1 Interrupt is assigned to interrupt line CC_int1 23 18 Reserved 0 Reads return 0 Writes have no effect 17 MTS...

Page 1349: ...Interrupt is assigned to interrupt line CC_int0 1 Interrupt is assigned to interrupt line CC_int1 5 RFNEL Receive FIFO not empty interrupt line 0 Interrupt is assigned to interrupt line CC_int0 1 Inte...

Page 1350: ...annel B interrupt enable 0 Interrupt is disabled 1 Transmission across boundary channel B interrupt is enabled 25 LTVBE Latest transmit violation channel B interrupt enable 0 Interrupt is disabled 1 L...

Page 1351: ...0 Interrupt is disabled 1 Uncorrectable RAM error interrupt is enabled 5 CCLE CHI command locked interrupt enable 0 Interrupt is disabled 1 CHI command locked interrupt is enabled 4 CCFE Clock correct...

Page 1352: ...1 26 Reserved 0 Reads return 0 Writes have no effect 25 MTSBE MTS received on channel B interrupt enable 0 Interrupt is disabled 1 MTS received on channel B interrupt is enabled 24 WUPBE Wakeup patter...

Page 1353: ...or changed interrupt is enabled 6 RFCLE Receive FIFO full interrupt enable 0 Interrupt is disabled 1 Receive FIFO overrun interrupt is enabled 5 RFNEE Receive FIFO not empty interrupt enable 0 Interru...

Page 1354: ...e 26 123 Interrupt Line Enable Register ILE offset_CC 40h 31 16 Reserved R 0 15 2 1 0 Reserved EINT R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 102 Interrupt Line Enable R...

Page 1355: ...register Figure 26 124 Timer 0 Configuration Register T0C offset_CC 44h 31 30 29 16 Reserved TOMO R 0 R W 0 15 14 8 7 2 1 0 Rsvd TOCC Reserved TOMS TORC R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write...

Page 1356: ...4 illustrate this register Figure 26 125 Timer 1 Configuration Register T1C offset_CC 48h 31 30 29 16 Reserved TIMC R 0 R W 2h 15 2 1 0 Reserved T1MS T1RC R 0 R W 0 LEGEND R Read only n value after re...

Page 1357: ...return 0 Writes have no effect 13 8 SCCV 0 3Fh Stopped cycle counter value State of the cycle counter when the stop watch event occurred 7 Reserved 0 Reads return 0 Writes have no effect 6 EINT1 Enabl...

Page 1358: ...Register 2 Register STPW2 Figure 26 127 and Table 26 106 illustrate this register Figure 26 127 Stop Watch Register 2 STPW2 offset_CC 50h 31 27 26 16 Reserved SSCVB R 0 R 0 15 11 10 0 Reserved SSCVA R...

Page 1359: ...TSM WUCS PTA R 0 R W 1 R W 1 R W 0 R W 0 R W 0 R W 1 R W 0 R W 0 15 11 10 9 8 7 6 4 3 0 CSA Rsvd TXSY TXST PBSY Reserved CMD R W 2h R 0 R W 0 R W 0 R 1 R 0 R W 0 LEGEND R W Read Write R Read only n v...

Page 1360: ...by hardware reset 21 WUCS Wakeup channel select With this bit the host selects the channel on which the communication controller sends the Wakeup pattern The communication controller ignores any atte...

Page 1361: ...h Eh Reserved Fh LOOPBACK MODE Controller Host Interface Command Vector The following gives more information about the controller host interface commands Reading CMD shows whether the last controller...

Page 1362: ...communication controller status vector register CLEAR_RAMS Sets bit CRAM in the message handler status register when called in DEFAULT_CONFIG or CONFIG state When called in any other state CMD will be...

Page 1363: ...EFAULT_CONFIG or CONFIG state only Figure 26 129 and Table 26 108 illustrate this register Figure 26 129 SUC Configuration Register 2 SUCC2 offset_CC 84h 31 28 27 24 23 21 20 16 Reserved LTN Reserved...

Page 1364: ...or NORMAL_PASSIVE state These must be identical in all nodes of a cluster Note The transition to HALT state is prevented if SUCC1 HCSE is not set 3 0 WCP 1 Fh Maximum without clock correction passive...

Page 1365: ...nodes of a cluster 15 14 BRP Baud rate prescaler These bits configure the baud rate on the FlexRay bus The baud rates listed below are valid with a sample clock of 80 MHz One bit time always consists...

Page 1366: ...ect 29 24 TXL Fh 3Ch bit times Wakeup symbol transmit low in bit times These bits configure the active low phase of the wakeup symbol The duration must be identical in all nodes of a cluster 23 16 TXI...

Page 1367: ...ese bits can be updated in DEFAULT_CONFIG or CONFIG state only Table 26 113 MHD Configuration Register MHDC Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reads return 0 Writes have n...

Page 1368: ...26 3 2 3 9 GTU Configuration Register 2 GTUC2 The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only Figure 26 136 and Table 26 115 illustrate this...

Page 1369: ...ary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration Must be identical in all nodes of a cluster 23 Reserved 0 Reads return 0 Writes...

Page 1370: ...guration Register 5 GTUC5 The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only Figure 26 139 and Table 26 118 illustrate this register Figure 26 13...

Page 1371: ...artup range in microticks Number of microticks constituting the expanded range of measured deviation for startup frames during integration 26 3 2 3 14 GTU Configuration Register 7 GTUC7 The communicat...

Page 1372: ...U Configuration Register 9 GTUC9 The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only Figure 26 143 and Table 26 122 illustrate this register Figur...

Page 1373: ...only Table 26 123 GTU Configuration Register 10 GTUC10 Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reads return 0 Writes have no effect 26 16 MRC 2h 783h T Maximum rate correction...

Page 1374: ...r CONFIG state only 23 19 Reserved 0 Reads return 0 Writes have no effect 18 16 EOC 0 7h T External offset correction in microticks Holds the external clock offset correction value to be applied by th...

Page 1375: ...nt wakeup attempt Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to EFAULT_CONFIG state 0 UNDEFINED No wakeup attempt since CONFIG state was left 1h RECEIVED_HEADER Set when t...

Page 1376: ...SET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or when entering READY state 6 FSI 0 1 Freeze status indicator Indicates that the POC has entered the HALT state due to CHI com...

Page 1377: ...Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 8 PTAC 0 1Fh Passive to active count Indicates the number of consecutive even odd cycle pairs that have passed with valid rate and...

Page 1378: ...Reserved 0 Reads return 0 Writes have no effect 10 0 SCCA 1h 7FFh Slot counter channel A Current slot counter value channel A The value is incremented by the communication controller and reset at the...

Page 1379: ...d internal rate correction value before limitation If the RCV value exceeds the limits defined by GTUC10 MRC flag SFS RCLR is set to 1 NOTE The external rate correction value is added to the limited r...

Page 1380: ...ction is below limit 1 Offset correction limit is reached 16 MOCS Missing offset correction signal The missing offset correction signal signals to the host that no rate correction can be performed bec...

Page 1381: ...annel B 9 SBNA Slot boundary violation during NIT channel A 0 No slot boundary violation is detected 1 Slot boundary violation during NIT is detected on channel A 8 SENA Syntax error during NIT channe...

Page 1382: ...state or enters STARTUP state Figure 26 154 and Table 26 133 illustrate this register Figure 26 154 Aggregated Channel Status Register ACS offset_CC 128h 31 16 Reserved R 0 15 13 12 11 10 9 8 7 5 4 3...

Page 1383: ...lot boundary violation is observed on channel A 3 CIA Communication indicator channel A One or more valid frames were received on channel A in slots that also contained any additional communication du...

Page 1384: ...ARTUP state Figure 26 155 and Table 26 134 illustrate this register Figure 26 155 Even Sync ID Registers ESIDn offset_CC 130h 168h 31 16 Reserved R 0 15 14 13 10 9 0 RXEB RXEA Reserved EID R 0 R 0 R 0...

Page 1385: ...TARTUP state Figure 26 156 and Table 26 135 illustrate this register Figure 26 156 Odd Sync ID Registers OSIDn offset_CC 170h 1A8h 31 16 Reserved R 0 15 14 13 10 9 0 RXOB RXOA Reserved OID R 0 R 0 R 0...

Page 1386: ...updates the NM vector at the end of each communication cycle as long as the communication controller is either in NORMAL_ACTIVE or NORMAL_PASSIVE state NMVn bytes exceeding the configured NM vector le...

Page 1387: ...rom message buffer 0 with the same payload data on both channels Note that the channel filter configuration for message buffer 0 resp message buffer 1 has to be chosen accordingly 0 Only message buffe...

Page 1388: ...Header Sections The maximum number of header sections is 128 This means a maximum of 128 message buffers can be configured The maximum length of the data sections is 254 bytes The length of the data...

Page 1389: ...Description 31 25 Reserved 0 Reads return 0 Writes have no effect 24 RNF Reject null frames If this bit is set received null frames are not stored in the FIFO 0 Null frames are stored in the FIFO 1 R...

Page 1390: ...Reserved 0 Reads return 0 Writes have no effect 12 2 MFID Mask Frame ID Filter 0 Corresponding frame ID filter bit is used for rejection filtering 1 Ignore corresponding frame ID filter bit 1 0 Reserv...

Page 1391: ...r If the message buffer is configured for single shot mode the respective TXR flag in the Transmission request register 1 4 TXRQ1 4 was reset Note MBT are reset when the communication controller leave...

Page 1392: ...munication controller leaves CONFIG state or enters STARTUP state Figure 26 163 and Table 26 143 illustrate this register Figure 26 163 Last Dynamic Transmit Slot LDTS offset_CC 314h 31 27 26 16 Reser...

Page 1393: ...ve FIFO overrun occurs the oldest message is overwritten with the actual received message In addition interrupt flag RFO in the Error Interrupt Register EIR is set The flag is cleared by the next FIFO...

Page 1394: ...t to header partition 7 TNSA Transmission Not Started Channel A This flag is set by the CC when the Message Handler was not ready to start a scheduled transmission on channel A at the action point of...

Page 1395: ...a message buffer s status MBS with respect to channel B 0 No overload condition occurred when updating MBS for channel B 1 MBS for channel B is not updated 0 SNUA Status not updated channel A This fla...

Page 1396: ...alue after reset Figure 26 167 Transmission Request Register 3 TXRQ3 offset_CC 328h 31 16 TXR 95 80 R 0 15 0 TXR 79 64 R 0 LEGEND R Read only n value after reset Figure 26 168 Transmission Request Reg...

Page 1397: ...mmunication controller leaves CONFIG state or enters STARTUP state Figure 26 170 through Figure 26 173 and Table 26 147 illustrate these registers Figure 26 170 New Data Register 4 NDAT4 offset_CC 33C...

Page 1398: ...s are reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the output buffer 1 The flags are set when a valid received dat...

Page 1399: ...31 16 MBS 95 80 R 0 15 0 MBS 79 64 R 0 LEGEND R Read only n value after reset Figure 26 176 Message Buffer Status Changed Register 2 MBSC2 offset_CC 344h 31 16 MBS 63 48 R 0 15 0 MBS 47 32 R 0 LEGEND...

Page 1400: ...0 FFh Step of Core Release Two digits BCD coded 19 16 YEAR 0 Fh Design Time Stamp Year One digit BCD coded 15 8 MON 0 FFh Design Time Stamp Month Two digits BCD coded 7 0 DAY 0 FFh Design Time Stamp...

Page 1401: ...ed and the data pointer need to be configured by bits PLC of the Write Header Section 2 WRHS2 and by bits DP of Write Header Section 3 WRHS3 All information required for acceptance filtering is taken...

Page 1402: ...ic message buffer the respective message buffer holds network management information If the bit is set in a dynamic message buffer the first two bytes of the payload segment may be used for message ID...

Page 1403: ...et Table 26 155 Write Header Section Register 2 WRHS2 Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reads return 0 Writes have no effect 22 16 PLC 0 7Fh Payload length configured Len...

Page 1404: ...Figure 26 183 Write Header Section Register 3 WRHS3 offset_CC 508h 31 16 Reserved R 0 15 11 10 0 Reserved DP R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 156 Write Header S...

Page 1405: ...buffer is released for transmission operation ongoing or finished 17 LDSS Load data section shadow 0 Data section is not updated 1 Data section is selected for transfer from input buffer to the messa...

Page 1406: ...red under IBRH and IBRS are also swapped Any write access to an Input Buffer Register while both IBSYS and IBSYH are set will cause the error flag IIBA in the Error Interrupt Register EIR to be set In...

Page 1407: ...d message buffer The data words DW n are read from the message RAM in reception order from DW 1 byte0 byte1 to DW PL DW PL number of data words as defined by the payload length configured in bits PLC...

Page 1408: ...TXM Transmission mode This bit is used to select the transmission mode 0 Continuous mode 1 Single shot mode 27 PPIT Payload preamble indicator transmit 0 Payload Preamble Indicator is not set 1 Paylo...

Page 1409: ...in the message buffer is truncated to the payload length configured if PLC even or else truncated to PLC 1 PLR PLC The received payload data is stored into the message buffers data section The remaini...

Page 1410: ...ID 1 Static segment Network management vector at the beginning of the payload Dynamic segment Message ID at the beginning of the payload 27 NFI Null frame indicator Is set to 1 after storage of the fi...

Page 1411: ...1 0 FTB FTA Rsvd MLST ESB ESA TCIB TCIA SVOB SVOA CEOB CEOA SEOB SEOA VFRB VFRA R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 26 163 Mess...

Page 1412: ...e condition is checked in static and dynamic slots 0 Bus activity is detected in the configured slot on channel A 1 No bus activity is detected in the configured slot on channel A 9 TCIB Transmission...

Page 1413: ...ication is set if a valid frame was received on channel B 0 No valid frame is received on channel B 1 Valid frame is received on channel B 0 VFRA Valid frame received on channel A A valid frame indica...

Page 1414: ...fer Command Mask Register OBCM Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads return 0 Writes have no effect 17 RDSH Read data section host 0 Data section is not read 1 Data sec...

Page 1415: ...ransfer from OBF host When the current transfer between Message RAM and OBF shadow has completed this is signaled by setting OBSYS back to 0 Any write access to OBCR 15 8 while OBSYS is set will cause...

Page 1416: ...ptions continued Bit Field Value Description 7 Reserved 0 Reads return 0 Writes have no effect 6 0 OBRS 0 7Fh Output buffer request shadow Number of source message buffer to be transferred from the me...

Page 1417: ...res the number of instantiations of the DCAN IP and the number of mailboxes supported on your specific device being used Topic Page 27 1 Overview 1418 27 2 CAN Blocks 1419 27 3 CAN Bit Timing 1421 27...

Page 1418: ...es for self test operation Direct access to Message RAM in test mode Supports Two interrupt lines Level 0 and Level 1 Others Automatic Message RAM initialization Automatic bus on after Bus Off state b...

Page 1419: ...upts or DMA requests 27 2 CAN Blocks The DCAN Module shown in Figure 27 1 comprises of the following basic blocks 27 2 1 CAN Core The CAN Core consists of the CAN Protocol Controller and the Rx Tx Shi...

Page 1420: ...odulated clock output from FMPLL is used as the VCLK source then VCLKA should be derived from an unmodulated clock source for example OSCIN source The clock source for VCLKA is selected by the Periphe...

Page 1421: ...Each segment consists of a specific number of time quanta The length of one time quantum tq which is the basic time unit of the bit time is given by the CAN_CLK and the Baud Rate Prescalers BRPE and B...

Page 1422: ...s Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus level at the previous sample point A synchronization may be done only if a recessive bit was sa...

Page 1423: ...t of 8 to 25 time quanta The length of the time quantum tq is defined by the Baud Rate Prescaler with tq Baud Rate Prescaler CAN_CLK Several combinations may lead to the desired bit time allowing iter...

Page 1424: ...be programmed into the register It is calculated using the following equation BRP CAN_CLK BAUD 1 TSEG1 TSEG2 37 27 3 2 3 Example for Bit Timing at High Baudrate In this example the frequency of CAN_C...

Page 1425: ...nfigured before it can participate on the CAN bus 27 4 1 DCAN RAM Initialization Through Hardware To start with a clean DCAN RAM the complete DCAN RAM has to be initialized with zeros and the ECC bits...

Page 1426: ...uration register Also note that the CAN module is also in initialization mode on hardware reset and during Bus Off Step 2 Set the CCE Configure Change Enable bit in the CAN Control Register The access...

Page 1427: ...bjects are deactivated by default You should configure the message object that are to be used to a particular identifier you can change the configuration of any message object or deactivate it when re...

Page 1428: ...ask bits are used for acceptance filtering Note If the UMask bit is set to 1 the message object s mask bits have to be programmed during initialization of the message object before MsgVal is set to 1...

Page 1429: ...me 1 IntPnd will be triggered after the successful transmission of a frame IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 This message object is the source of an in...

Page 1430: ...essage RAM Addressing in Debug Suspend and RDA Mode Message Object Number Base Address Offset Word Number Debug Suspend mode see Section 27 5 3 RDA mode see Section 27 5 4 1 0x0020 1 Reserved Data Byt...

Page 1431: ...Mode Test bit in CAN control register is set the CPU has direct access to the Message RAM Due to the 32 bit bus structure the RAM is split into word lines to support this feature The CPU has access to...

Page 1432: ...CC bits of the last implemented message object are located As shown in Figure 27 7 the ECC bits for the last implemented Message Object here 128 are located at offset 0x1000 the ECC bits for Message O...

Page 1433: ...see Section 27 5 4 For the Message RAM Base address refer to the device datasheet A complete message object see Section 27 5 1 or parts of the message object may be transferred between the Message RAM...

Page 1434: ...ster Sets 1 and 2 The Command Register addresses the desired message object in the Message RAM and specifies whether a complete message object or only parts should be transferred The data transfer is...

Page 1435: ...IF3 Update Enable 5 0x16C IF3 Update Enable 8 IF3 Update Enable 7 The automatic update functionality can be programmed for each message object see IF3 Update Enable Register Section 27 17 33 All valid...

Page 1436: ...Frames Setting TxRqst for a Receive Object will cause the transmission of a Remote Frame with the same identifier as the Data Frame for which this receive Object is configured 27 7 3 Configuration of...

Page 1437: ...a Length Code The data bytes of the message object will remain unchanged If the RxIE bit is set the IntPnd bit will be set when a received Remote Frame is accepted and stored in the message object 27...

Page 1438: ...ed by IF1 IF2 registers when priority is same or higher as message the object found by last scanning Handling of TxRqst flags Handling of interrupt flags The Message Handler registers contains status...

Page 1439: ...of a Data Frame if in the matching Transmit Object the RmtEn bit is set 27 8 4 Updating a Transmit Object The CPU may update the data bytes of a Transmit Object any time via the IF1 IF2 Interface Reg...

Page 1440: ...s already set MsgLst is set to indicate that the previous data supposedly not seen by the CPU is lost If the RxIE bit is set the IntPnd bit is set causing the Interrupt Register to point to this messa...

Page 1441: ...matching to a FIFO Buffer are stored into a message object of this FIFO Buffer starting with the message object with the lowest message number When a message is stored into a message object of a FIFO...

Page 1442: ...ntPnd Read IF1 IF2 message control NewDat 1 Read data from IF1 IF2 Data A B EoB 1 Next Message Number in this FIFO Buffer Yes No Yes No Message interrupt Interrupt Handling Message Number interrupt id...

Page 1443: ...CPU may read or write each message at any time via the Interface Registers as the Message Handler guarantees data consistency in case of concurrent accesses for reconfiguration see Section 27 7 6 If...

Page 1444: ...Int1ID in the Interrupt Register see Section 27 17 5 When no interrupt is pending the register will hold the value zero Each interrupt line remains active until the dedicated field in the Interrupt R...

Page 1445: ...ed at each CAN frame independent of bus errors or valid CAN communication and also independent of the Message RAM configuration Status Change interrupts can only be routed to interrupt line DCAN0INT t...

Page 1446: ...ishes all transmit requests of the message objects When all requests are done the DCAN waits until a bus idle state is recognized Then it will automatically set the Initbit to indicate that the global...

Page 1447: ...these messages may be sent 27 12 2 Wakeup From Local Power Down There are two ways to wake up the DCAN from local power down mode 1 The application could wake up the DCAN module manually by clearing t...

Page 1448: ...lication set Init 0 CAN bus activity WUBA bit D_CAN set PDA bit 0 set PDR bit 0 set WakeUpPnd bit 1 CAN_INTR 1 if enabled set Init bit 0 Wait for 11 recessive bits END 1 GIO Support www ti com 1448 SP...

Page 1449: ...e that all message transfers are finished before setting the Init bit to 1 27 14 1 Silent Mode The Silent Mode may be used to analyze the traffic on the CAN bus without affecting it by sending dominan...

Page 1450: ...input pin is disregarded by the CAN Core Transmitted messages still can be monitored at the CAN_TX pin In order to be independent from external stimulation the CAN Core ignores acknowledge errors rece...

Page 1451: ...the Tx pin itself and the signal path from Tx pin back to CAN Core When External Loop Back Mode is selected the input of the CAN core is connected to the input buffer of the Tx pin With this configura...

Page 1452: ...nation of Loop Back Mode with Silent Mode Figure 27 19 CAN Core in Loop Back Combined with Silent Mode 27 14 5 Software Control of CAN_TX Pin Four output functions are available for the CAN transmit p...

Page 1453: ...ingle bit error has occurred will be indicated in the ECC single bit Error Code Register When single bit error correction is disabled the message object data can be read by the host CPU independently...

Page 1454: ...hold the values shown in the register descriptions The base address for the control registers is FFF7 DC00h for DCAN1 FFF7 DE00h for DCAN2 FFF7 E000h for DCAN3 and FFF7 E200h for DCAN4 Additionally t...

Page 1455: ...r Section 27 17 22 E4h DCAN INTMUX78 Interrupt Multiplexer 78 Register Section 27 17 22 100h DCAN IF1CMD IF1Command Register Section 27 17 23 104h DCAN IF1MSK IF1 Mask Register Section 27 17 24 108h D...

Page 1456: ...0 R W 0 R W 0 R W 0 R W 1 LEGEND R W Read Write R Read only WP Write protected by Init bit n value after reset Table 27 7 CAN Control Register DCAN CTL Field Descriptions Bit Field Value Description...

Page 1457: ...is bit will automatically get cleared after execution of SW reset after one VBUSP clock cycle Note To execute SW reset the following procedure is necessary 1 Set Init bit to shut down CAN communicatio...

Page 1458: ...d EWarn bits can generate an interrupt at DCAN0INT line and affect the Interrupt Register 2 SIE Status change interrupt enable 0 Disabled WakeUpPnd RxOk TxOk and LEC bits cannot generate an interrupt...

Page 1459: ...ved 0 These bits are always read as 0 Writes have no effect 10 PDA Local power down mode acknowledge 0 DCAN is not in local power down mode 1 Application request for setting DCAN to local power down m...

Page 1460: ...d will be cleared to 0 when a message has been transferred reception or transmission without error 0 No Error 1h Stuff Error More than five equal bits in a row have been detected in a part of a receiv...

Page 1461: ...eset Table 27 9 Error Counter Register DCAN ERRC Field Descriptions Bit Field Value Description 31 16 Reserved 0 These bits are always read as 0 Writes have no effect 15 RP Receive Error Passive 0 The...

Page 1462: ...ription 31 20 Reserved 0 These bits are always read as 0 Writes have no effect BRPE 0 Fh Baud Rate Prescaler Extension Valid programmed values are 0 to 15 By programming BRPE the Baud Rate Prescaler c...

Page 1463: ...rrupt with the highest priority The DCAN1INT interrupt line remains active until Int1ID reaches value 0 the cause of the interrupt is reset or until IE1 is cleared A message interrupt is cleared by cl...

Page 1464: ...8 Reserved RDA EXL R 0 R WP 0 R WP 0 7 6 5 4 3 2 0 Rx Tx LBack Silent Reserved R U R WP 0 R WP 0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write Protected by Test bit n value after reset U Undef...

Page 1465: ...Field Value Description 31 11 Reserved 0 These bits are always read as 0 Writes have no effect 10 8 Word Number 0 Word Number is reserved and it will always read as 0 7 0 Message Number 1h FFh Messag...

Page 1466: ...ECC RAM is enabled Ah Diagnostic mode is disabled single bit and double bit errors are shown only in the ECC Control and Status register All other values Reserved 27 17 10 ECC Diagnostic Status Regist...

Page 1467: ...r event CAN_SERR signal 5h SECDED single bit error event is disabled single bit errors are not signaled with a high pulse on DCAN_SERR signal All other values SECDED single bit error event is enabled...

Page 1468: ...n ECC single bit error is detected the highest word number with an ECC single bit error is displayed After an ECC single bit error is detected the register holds the last error code until power is rem...

Page 1469: ...bit counter that starts to count down to 0 when the module goes Bus Off The counter will be reloaded with the preload value of the ABO_TIME register after this phase 27 17 14 Transmission Request X R...

Page 1470: ...27 34 Transmission Request 12 Register DCAN TXRQ12 offset 88h 31 0 TxRqst 32 1 R 0 LEGEND R Read only n value after reset Figure 27 35 Transmission Request 34 Register DCAN TXRQ34 offset 8Ch 31 0 TxRq...

Page 1471: ...jects If at least on of the NewDat bits of these message objects are set the corresponding bit in the New Data X Register will be set Figure 27 38 New Data X Register DCAN NWDAT X offset 98h 31 16 Res...

Page 1472: ...WDAT12 offset 9Ch 31 0 NewDat 32 1 R 0 LEGEND R Read only n value after reset Figure 27 40 New Data 34 Register DCAN NWDAT34 offset A0h 31 0 NewDat 64 33 R 0 LEGEND R Read only n value after reset Fig...

Page 1473: ...If at least one of the IntPnd bits of these message objects are set the corresponding bit in the Interrupt Pending X Register will be set Figure 27 43 Interrupt Pending X Register DCAN INTPND X offse...

Page 1474: ...ssion Figure 27 44 Interrupt Pending 12 Register DCAN INTPND12 offset B0h 31 0 IntPnd 32 1 R 0 LEGEND R Read only n value after reset Figure 27 45 Interrupt Pending 34 Register DCAN INTPND34 offset B4...

Page 1475: ...ects If at least one of the MsgVal bits of these message objects are set the corresponding bit in the Message Valid X Register will be set Figure 27 48 Message Valid X Register DCAN MSGVAL X offset C0...

Page 1476: ...27 49 Message Valid 12 Register DCAN MSGVAL12 offset C4h 31 0 MsgVal 32 1 R 0 LEGEND R Read only n value after reset Figure 27 50 Message Valid 34 Register DCAN MSGVAL34 offset C8h 31 0 MsgVal 64 33...

Page 1477: ...27 53 Interrupt Multiplexer 12 Register DCAN INTMUX12 offset D8h 31 0 IntMux 32 1 R W 0 LEGEND R W Read Write n value after reset Figure 27 54 Interrupt Multiplexer 34 Register DCAN INTMUX34 offset D...

Page 1478: ...e second transfer will start after the first one has been completed NOTE While Busy bit is one IF1 IF2 Register sets are write protected For debug support the auto clear functionality of the IF1 IF2 C...

Page 1479: ...to the corresponding IF1 IF2 Register set Direction Write The Message Control bits will be transferred from the IF1 IF2 Register set to the message object addressed by Message Number Bits 7 0 If the T...

Page 1480: ...ts 7 0 IF1 IF2 Register set will be write protected The bit is cleared after read write action has finished 14 DMA Active Activation of DMA feature for subsequent internal IF1 IF2 update 0 DMA request...

Page 1481: ...k 15 0 R WP FFFFh LEGEND R W Read Write R Read WP Protected Write protected by Busy bit n value after reset Table 27 26 IF1 IF2 Mask Register Field Descriptions Bit Field Value Description 31 MXtd Mas...

Page 1482: ...and Direction receive Data Frame or Direction transmit Remote Frame Extended frames can be stored only in message objects with Xtd 1 standard frames in message objects with Xtd 0 If a received messag...

Page 1483: ...n operation For reconfiguration of message objects during normal operation see Section 27 7 6 and Section 27 7 7 30 Xtd Extended identifier 0 The 11 bit standard identifier is used for this message ob...

Page 1484: ...protected Figure 27 63 IF1 Message Control Register DCAN IF1MCTL offset 10Ch 31 16 Reserved R 0 15 14 13 12 11 10 9 8 NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst R WP 0 R WP 0 R WP 0 R WP 0 R WP...

Page 1485: ...grammed during initialization of the message object before MsgVal is set to 1 11 TxIE Transmit interrupt enable 0 IntPnd will not be triggered after the successful transmission of a frame 1 IntPnd wil...

Page 1486: ...ta 2 R WP 0 R WP 0 15 8 7 0 Data 1 Data 0 R WP 0 R WP 0 LEGEND R W Read Write WP Protected Write protected by Busy bit n value after reset Figure 27 66 IF1 Data B Register DCAN IF1DATB offset 114h 31...

Page 1487: ...of the current read cycle can be observed via status flags Bits 12 8 An interrupt request may be generated by the IF3Upd flag if the DE3 bit of DCAN CTL register is set See the device data sheet to fi...

Page 1488: ...Mask section still has data to read 7 5 Reserved 0 These bits are always read as 0 Writes have no effect 4 Data B Data B read observation 0 Data B section does not need to be read 1 Data B section has...

Page 1489: ...ring 1 The extended identifier bit IDE is used for acceptance filtering Note When 11 bit standard identifiers are used for a message object the identifiers of received Data Frames are written into bit...

Page 1490: ...it resets bit Init in the CAN Control Register MsgVal must also be reset if the messages object is no longer used in operation For reconfiguration of message objects during normal operation see Sectio...

Page 1491: ...r stored a new message into this object when NewDat was still set so the previous message has been overwritten 13 IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 Thi...

Page 1492: ...ngth Code 0 8h Data Frame has 0 8 data bits 9h Fh Data Frame has 8 data bytes Note The Data Length Code of a message object must be defined the same as in all the corresponding objects with the same i...

Page 1493: ...Enable 12 Register DCAN IF3UPD12 offset 160h 31 0 IF3UpdEn 32 1 R W 0 LEGEND R W Read Write n value after reset Figure 27 76 IF3 Update Enable 34 Register DCAN IF3UPD34 offset 164h 31 0 IF3UpdEn 64 3...

Page 1494: ...0 1 CAN_TX Pullup is selected when pull logic is active PD 0 17 PD CAN_TX pull disable This bit is only active when CAN_TX is configured to be an input 0 CAN_TX pull is active 1 CAN_TX pull is disable...

Page 1495: ...WP 0 15 4 3 2 1 0 Reserved Func Dir Out In R 0 R WP 0 R WP 0 R WP 0 R U LEGEND R W Read Write R Read WP Protected Write protected by Init bit D value is device dependent n value after reset Table 27 3...

Page 1496: ...s an output Forced to 0 if Init bit of CAN control register is reset 1 Out CAN_RX data out write This bit is only active when CAN_RX pin is configured to be in GIO mode RIOC Func 0 and configured to b...

Page 1497: ...hift register used for high speed communication between external peripherals or other microcontrollers Throughout this chapter all references to SPI also apply to MibSPI MibSPIP unless otherwise noted...

Page 1498: ...iple programmable chip selects The MibSPI has a programmable Multi buffer array that enables programed transmission to be completed without CPU intervention The buffers are combined in different trans...

Page 1499: ...er NOBREAK buffer NOTE SIMO Slave In Master Out Pin SOMI Slave Out Master In Pin SPICS SPI Chip Select Pin SPIENA SPI Enable Pin 28 1 2 Pin Configurations The SPI supports data connections as shown in...

Page 1500: ...s the basic operation principle of the SPI mode and the MibSPI mode operation of the device 28 2 1 SPI Mode The SPI can be configured via software to operate as either a master or a slave The MASTER b...

Page 1501: ...al Peripheral Interface Module MibSPI with Parallel Pin Option MibSPIP Figure 28 1 SPI Functional Logic Diagram 28 2 1 2 Data Flow and Handling for TX and RX 28 2 1 2 1 Data Sequencing when SPIDAT0 or...

Page 1502: ...receive interrupt if enabled is generated The RXEMPTY flag in SPIBUF is cleared at the same time If SPIBUF is already full at the end of receive completion the RX shift register contents is copied to...

Page 1503: ...ughput of the SPI transfer is increased in Master mode of operation In case of Slave mode after the Receive data is copied to the RX RAM Sequencer waits for the next active Chip Select trigger to fetc...

Page 1504: ...egister is ignored DMA source or destination should be only the multi buffer RAM and not SPIDAT0 SPIDAT1 or SPIBUF register as in case of compatibility mode DMA The MibSPI offers up to eight DMA chann...

Page 1505: ...urred for transmit or for receive A programmer can also choose to group all of the error interrupts into one interrupt line and both TX empty and RX full interrupts into another interrupt line using t...

Page 1506: ...t will be generated indicating an overrun condition The error interrupts are enabled and prioritized independently from each other but the vector generated by the SPI will be the same if multiple erro...

Page 1507: ...erial clock on the SPICLK pin Data is transmitted on the SPISIMO pin and received on the SPISOMI pin see Figure 28 6 Data written to the shift register SPIDAT0 SPIDAT1 initiates data transmission on t...

Page 1508: ...t signal is used to select a specific slave In slave mode the chip select signal is used to enable and disable the transfer Chip select functionality is enabled by setting one of the SPICS pins as a c...

Page 1509: ...SPIENA pin is in high impedance mode ENABLE_HIGHZ 1 the slave will put SPIENA into the high impedance once it completes receiving a new character If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0...

Page 1510: ...low when new data is written to the slave shift register and the slave has been selected by the master SPICS is low If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0 the slave SPI drives this pin...

Page 1511: ...abled individually for each data format If a received parity bit does not match with the locally calculated parity bit the parity error flag PARITYERR is set and an interrupt is asserted if enabled Si...

Page 1512: ...delay and the polarity rising edge falling edge of the clock The data input and output edges depend on the values of both POLARITY and PHASE as shown in Table 28 3 Table 28 3 Clocking Modes POLARITY...

Page 1513: ...ling edge of SPICLK Input data is latched on the rising edge of SPICLK Write SPIDAT SPISIMO SPISOMI receive sample MSB D6 D5 D4 D3 D2 D1 D0 LSB D6 D5 D4 D3 D2 D1 D7 1 2 3 4 5 6 7 8 SPICLK www ti com B...

Page 1514: ...ock polarity 0 Clock phase 0 Clock phase 1 Basic Operation www ti com 1514 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Periphe...

Page 1515: ...e SPICS pins at the same time which enables encoded chip selects from 0 to 16 To use encoded chip selects all 6 chip select lines have to be connected to each slave device and each slave needs to have...

Page 1516: ...Finished to ENA Pin Inactive Time Out T2EDELAY T2EDELAY is used in master mode only It defines a time out value as a multiple of SPI clock before the ENAble signal has to become inactive and after the...

Page 1517: ...after the C2TDELAY completes This should be taken into consideration to determine an optimum value of C2EDELAY 28 2 6 5 Multiple Transfers to Same Slave and Variable Chip Select Setup and Hold Timing...

Page 1518: ...chip select pins will not be deasserted after the completion of this word If the next word to transmit has the same chip select number CSNR value the chip select pins will be maintained until the comp...

Page 1519: ...gth must be set as 16 bits Only module MIBSPIP5 supports Parallel Mode This feature increases throughput by 2 for 2 pins by 4 for 4 pins or by 8 for 8 pins Parallel mode supports the following feature...

Page 1520: ...LTIPLEXER Parallel mode 0 SOMI7 SOMI6 SOMI5 SOMI4 SOMI3 SOMI2 SOMI1 SOMI0 DEMULTIPLEXER Basic Operation www ti com 1520 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instrumen...

Page 1521: ...d SIMO pin mapping when the SPI is used in parallel mode 1 2 4 8 pin mode MSB first NOTE MSB first or LSB first can be configured using the SHIFTDIRx bit of the SPIFMTx registers Table 28 4 Pin Mappin...

Page 1522: ...B First Table 28 6 and Table 28 7 describe the SIMO and SOMI pin mapping when SPI is used in parallel mode 1 2 4 8 pin mode LSB first Table 28 6 Pin Mapping for SIMO Pin with LSB First Parallel Mode S...

Page 1523: ...MI 0 or vice versa in slave mode After writing to the SPIDAT0 SPIDAT1 register the bits 15 and 7 will be output on SIMO 1 and SIMO 0 on the rising edge if SPICLK With the falling clock edge of the SPI...

Page 1524: ...ce versa in slave mode After writing to SPIDAT1 SPIDAT0 the bits 15 11 7 and 3 will be output on SIMO 3 SIMO 2 SIMO 1 and SIMO 0 on the rising edge of SPICLK With the falling clock edge of the SPICLK...

Page 1525: ...4 SIMO 3 SIMO 2 SIMO 1 and SIMO 0 on the rising edge of SPICLK On the falling clock edge of the SPICLK the received data on SOMI 8 SOMI 7 SOMI 6 SOMI 5 SOMI 4 SOMI 3 SOMI 2 SOMI 1 and SOMI 0 will be l...

Page 1526: ...ect the MibSPI is deselected that is Transfer Group 15 is not available in slave mode The remaining chip select pins should stay in GPIO mode In slave mode the fields like trigger source and trigger e...

Page 1527: ...to the Rx buffer and updates the status field NOTE If all the Transfer Groups are not needed the number of SPICS pins that need to be in functional mode could be reduced to 3 2 or 1 by using the SPIPC...

Page 1528: ...om the PSTART of the respective TGxCTRL register Sequencer requests for the selected buffer through the Multi buffer Control Logic and once it receives the data it reads the control fields to determin...

Page 1529: ...n entering such modes to ensure that a valid state is entered when low power mode is active Application software must ensure that a low power mode is not entered during a data transfer 28 2 9 Safety F...

Page 1530: ...f the SPIENA pin by the slave while the character counter is not overflowed then an error flag is set to indicate a data length error This can be caused by a slave receiving extra clocks for example d...

Page 1531: ...nput output buffers or digital loopback internal to the SPI module With Input Output Loopback all functional features of the SPI can be tested Transmit data is fed back through the receive data line s...

Page 1532: ...chip select pins are the triggers for various TGs Enabling the IOLPBK mode by writing 0xA to the IOLPBTSTENA bits of the IOLPBKTSTCR register triggers TG0 by driving SPICS to 0 The actual number of c...

Page 1533: ...SPIENA pins for SPI functionality by setting the corresponding bit in SPIPC0 register Configure the module to function as Master or Slave using CLKMOD and MASTER bits Configure the required SPI data f...

Page 1534: ...ing SPIDELAY register Check for BUFINITACTIVE bit to be active before configuring MIBSPI RAM From Device Power On it take Number of Buffers Peripheral clock period to initialize complete RAM Enable th...

Page 1535: ...3 8 20h SPIPC3 SPI Pin Control Register 3 Section 28 3 9 24h SPIPC4 SPI Pin Control Register 4 Section 28 3 10 28h SPIPC5 SPI Pin Control Register 5 Section 28 3 11 2Ch SPIPC6 SPI Pin Control Registe...

Page 1536: ...SPI Extended Prescale Register 2 Section 28 3 45 140h ECCDIAG_CTRL ECC Diagnostic Control Register Section 28 3 46 144h ECCDIAG_STAT ECC Diagnostic Status Register Section 28 3 47 148h SBERRADDR1 Sin...

Page 1537: ...Reserved 0 Reads return 0 Writes have no effect 16 LOOPBACK Internal loop back test mode The internal self test option can be enabled by setting this bit If the SPISIMO and SPISOMI pins are configure...

Page 1538: ...4 3 2 1 0 Reserved RXOVRNINT ENA Reserved BITERR ENA DESYNC ENA PARERR ENA TIMEOUT ENA DLENERR ENA R 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Tab...

Page 1539: ...7 Reserved 0 Reads return 0 Writes have no effect 6 RXOVRNINTENA Overrun interrupt enable 0 Overrun interrupt will not be generated 1 Overrun interrupt will be generated 5 Reserved 0 Reads return 0 Wr...

Page 1540: ...Reads return 0 Writes have no effect 6 RXOVRNINTLVL Receive overrun interrupt level 0 Receive overrun interrupt is mapped to interrupt line INT0 1 Receive overrun interrupt is mapped to interrupt lin...

Page 1541: ...ters or buffer handling Note If the SPIFLG register is read while the multi buffer RAM is being initialized the BUF INIT ACTIVE bit will be read as 1 If SPIFLG is read after the internal automatic buf...

Page 1542: ...NTVECT1 register when there is a receive buffer overrun interrupt Writing a 1 to RXOVRNINTFLG in the SPI Flag Register SPIFLG itself Writing a 0 to SPIEN Reading the data field of the SPIBUF register...

Page 1543: ...is set This flag can be cleared by one of the following methods Write a 1 to this bit Clear the SPIEN bit to 0 0 No parity error detected 1 A parity error occurred 1 TIMEOUTFLG Time out caused by non...

Page 1544: ...the value of bit 11 will control the SPISOMI 0 pin The read value of Bit 24 always reflects the value of bit 11 0 SPISOMI x pin is a GIO pin 1 SPISOMI x pin is a SPI functional pin 23 16 SIMOFUN Slave...

Page 1545: ...er 1 SPIPC1 NOTE Register bits vary by device Register bits 31 24 and 23 16 of this register reflect the number of SIMO SOMI data lines per device On devices with 8 data line support all of bits 31 to...

Page 1546: ...d as a SPI functional pin the I O direction is determined by the MASTER bit in the SPIGCR1 register 0 SPISOMI0 pin is an input 1 SPISOMI0 pin is an output 10 SIMODIR0 SPISIMO0 direction This bit contr...

Page 1547: ...0 SCSDIN R W U LEGEND R W Read Write R Read only U value is undefined n value after reset Table 28 16 SPI Pin Control Register 2 SPIPC2 Field Descriptions Bit Field Value Description 31 24 SOMIDIN SP...

Page 1548: ...will have priority over bit 24 0 Current value on SPISOMIx pin is logic 0 1 Current value on SPISOMIx pin is logic 1 23 16 SIMODOUT SPISIMOx data out write This bit is only active when the SPISIMOx p...

Page 1549: ...are implemented On devices with less than 8 data lines only a subset of these bits are available Unimplemented bits return 0 upon read and are not writable Figure 28 41 SPI Pin Control Register 4 SPIP...

Page 1550: ...O0 is logic 0 Write No effect 1 Read SPISIMO0 is logic 1 Write Logic 1 is placed on SPISIMO0 pin if it is in general purpose output mode 9 CLKSET SPICLK data out set This bit is only active when the S...

Page 1551: ...in If a 32 bit write is performed bit 11 will have priority over bit 24 0 Read The current value on SOMIDOUTx is 0 Write No effect 1 Read The current value on SOMIDOUTx is 1 Write Logic 0 is placed on...

Page 1552: ...ffect 1 Read The current value on SPIENA is 1 Write Logic 0 is placed on SPIENA pin if it is in general purpose output mode 7 0 SCSCLR SPICS data out clear This bit is only active when the SPICS pin i...

Page 1553: ...ct 11 SOMIPDR0 SOMI0 open drain enable This bit enables open drain capability for SOMI0 if the following conditions are met SOMI0 pin configured in GIO mode as output pin Output value on SPISOMI0 pin...

Page 1554: ...31 24 SOMIDIS SOMIx pull control disable This bit disables pull control capability for each SOMIx pin if it is in input mode regardless of whether it is in functional or GIO mode Note Bit 11 or bit 24...

Page 1555: ...pin is disabled 28 3 14 SPI Pin Control Register 8 SPIPC8 NOTE Register bits vary by device Register bits 31 24 and 23 16 of this register reflect the number of SIMO SOMI data lines per device On dev...

Page 1556: ...Pull down on the SPIENA pin 1 Pull up on the SPIENA pin 7 0 SCSPSEL SPICS pull select This bit selects the type of pull logic at the SPICS pin 0 Pull down on the SPICS pin 1 Pull up on the SPICS pin...

Page 1557: ...the end of a transfer until a control field with new data and control information is loaded into SPIDAT1 If the new chip select number equals the previous one the active chip select signal is extended...

Page 1558: ...is empty If the shift register is not empty then they are held in TXBUF SPIEN must be set to 1 before this register can be written to Writing a 0 to SPIEN forces the lower 16 bits of SPIDAT1 to 0x000...

Page 1559: ...CS 0 0h No chip select pin is active 20h x 1h x 21h x x 2h x 22h x x 3h x x 23h x x x 4h x 24h x x 5h x x 25h x x x 6h x x 26h x x x 7h x x x 27h x x x x 8h x 28h x x 9h x x 29h x x x Ah x x 2Ah x x...

Page 1560: ...OVR is set Overruns always occur to RXBUF not to SPIBUF the contents of SPIBUF are overwritten only after it is read by the Peripheral VBUSP master CPU DMA or other host processor If enabled the RXOVR...

Page 1561: ...e the desync flag is always guaranteed to be for the current buffer Note This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read 0 No slave desynchronization is detected 1 A sla...

Page 1562: ...SPIDELAY Figure 28 50 SPI Delay Register SPIDELAY offset 48h 31 24 23 16 C2TDELAY T2CDELAY R W 0 R W 0 15 8 7 0 T2EDELAY C2EDELAY R W 0 R W 0 LEGEND R W Read Write n value after reset Table 28 28 SPI...

Page 1563: ...ing one or more clock edges it becomes de synchronized In this case although the master has finished the data transfer the slave is still waiting for the missed clock pulses and the ENA signal is not...

Page 1564: ...A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Peripheral Interface Module MibSPI with Parallel Pin Option MibSPIP Figure 28 51 Example...

Page 1565: ...erved CSDEF R 0 R W FFh LEGEND R W Read Write R Read only n value after reset Table 28 29 SPI Default Chip Select Register SPIDEF Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads r...

Page 1566: ...f each transmitted word At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag If the parity bits do not match the RXERR flag is set in...

Page 1567: ...reset and reconfigured if clock phase polarity needs to be switched In summary SPI format switching is not fully supported in slave mode Even while using chip select pins the polarity of SPICLK can b...

Page 1568: ...f interrupt suspended or finished 11h Error Interrupt pending The lower half of SPIFLG contains more details about the type of error 13h The pending interrupt is a Receive Buffer Overrun interrupt 12h...

Page 1569: ...1 INTVECT1 Bit Field Value Description 31 6 Reserved 0 Reads return 0 Writes have no effect 5 1 INTVECT1 INTVECT1 Interrupt vector for interrupt line INT1 Returns the vector of the pending interrupt a...

Page 1570: ...ity transfer group A read from INTVECT1 automatically causes the next highest priority transfer group s interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to get loaded in...

Page 1571: ...control is used for this pin 23 17 Reserved 0 Reads return the value that was last written Writes have no effect 16 SIMOSRS0 SPI2 SPISIMO 0 slew control This bit controls between the fast or slow slew...

Page 1572: ...Reserved MODCLKPOL3 MMODE3 PMODE3 R 0 R WP 0 R WP 0 R WP 0 23 22 21 20 18 17 16 Reserved MODCLKPOL2 MMODE2 PMODE2 R 0 R WP 0 R WP 0 R WP 0 15 14 13 12 10 9 8 Reserved MODCLKPOL1 MMODE1 PMODE1 R 0 R WP...

Page 1573: ...mine whether the SPI MibSPI operates with 1 2 4 or 8 data lines 0 Normal operation 1 data line MMODE2 should be set to 000 1h 2 data line mode MMODE2 should be set to 000 2h 4 data line mode MMODE2 sh...

Page 1574: ...o option is supported by the module 0 1 data line mode default PMODE0 should be set to 00 1h 2 data line mode PMODE0 should be set to 00 2h 3 data line mode PMODE0 should be set to 00 3h 4 data line m...

Page 1575: ...ritable by the CPU 1 The whole of multi buffer RAM is fully accessible for read write by the CPU Note The RX RAM ACCESS bit remains 0 after reset and it should remain set to 0 at all times except when...

Page 1576: ...t Table 28 36 TG Interrupt Enable Set Register TGITENST Field Descriptions Bit Field Value Description 31 16 SETINTENRDY n TG interrupt set enable when transfer finished Bit 16 corresponds to TG0 bit...

Page 1577: ...ield Descriptions Bit Field Value Description 31 16 CLRINTENRDY n TG interrupt clear disabled when transfer finished Bit 16 corresponds to TG0 bit 17 corresponds to TG1 and so on 0 Read The TGx comple...

Page 1578: ...offset 7Ch 31 16 SETINTLVLRDY 15 0 R W 0 15 0 SETINTLVLSUS 15 0 R W 0 LEGEND R W Read Write n value after reset Table 28 38 Transfer Group Interrupt Level Set Register TGITLVST Field Descriptions Bit...

Page 1579: ...offset 80h 31 16 CLRINTLVLRDY 15 0 R W 0 15 0 CLRINTLVLSUS 15 0 R W 0 LEGEND R W Read Write n value after reset Table 28 39 Transfer Group Interrupt Level Clear Register TGITLVCR Field Descriptions Bi...

Page 1580: ...automatically clears the interrupt flag bit INTFLGRDYx referenced by the vector number given by INTVECT0 INTVECT1 bits if the SUSPEND 0 1 bit in the vector registers is 0 0 Read No transfer completed...

Page 1581: ...enable 0 The internal tick counter is disabled The counter value remains unchanged Note When the tick counter is disabled the trigger signal is forced low 1 The internal tick counter is enabled and i...

Page 1582: ...ncer Note The number of transfer groups varies by device 11h 1Fh Invalid values 23 16 Reserved 0 Reads return 0 Writes have no effect 15 8 LPEND 0 FFh Last TG end pointer Usually the TG end address PE...

Page 1583: ...t enables the TG again This one shot mode ensures that after one group transfer the host has enough time to read the received data and to provide new transmit data 29 PRSTx TGx pointer reset mode Conf...

Page 1584: ...the sequencer continues with the same TG until it is completed 0 never Never trigger TGx This is the default value after reset 1h rising edge A rising edge 0 to 1 at the selected trigger source TRIGSR...

Page 1585: ...ice for example HET I O channel event pin Dh EXT12 External trigger source 12 The actual source varies per device for example HET I O channel event pin Eh EXT13 External trigger source 13 The actual s...

Page 1586: ...more DMA requests are generated In conjunction with NOBRKx a burst transfer can be initiated without any other transfer through another buffer 30 24 BUFIDx 0 7Fh Buffer utilized for DMA transfer BUFID...

Page 1587: ...from the buffer referenced by BUFIDx without a data transfer from any other buffer The sequencer remains at the DMA buffer until ICOUNTx 1 transfers have been processed For example this can be used to...

Page 1588: ...sponding DMA channel If NOBRKx is set ICOUNTx defines the number of DMA transfers that are performed in one sequence without a transfer from any other buffer 15 0 COUNTx 0 FFFFh Actual number of remai...

Page 1589: ...rved 0 Reads return 0 Writes have no effect 0 LARGE COUNT Select either the 16 bit DMAxCOUNT counters or the smaller counters in DMAxCTRL 0 Select the DMAxCTRL counters Writes to the DMAxCTRL register...

Page 1590: ...he values are not updated into this field The state of the feature remains unchanged Read Returns the current value of the field 23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 EDAC_MODE T...

Page 1591: ...Write No effect 1 Read Single bit error is detected in RXRAM and the address is captured in SBERRADDR1 register Write Clears the bit 8 SBE_FLG0 Single Bit Error in TXRAM This flag indicates if a sing...

Page 1592: ...from 000h 3FFh The register does not clear its contents during and after any of the module level resets System level resets or even Power on Reset NOTE A read to UERRADDR1 register will clear the UER...

Page 1593: ...eral Interface Module MibSPI with Parallel Pin Option MibSPIP Table 28 50 Effect of BIG_ENDIAN Port on UERRADDR1 1 0 Bits Endianness Fault Location is Among the RAM Bits 1 Big Endian 0 Little Endian U...

Page 1594: ...ter does not clear its contents during and after any of the module level resets System level resets or even Power on Reset NOTE A Read to UERRADDR0 register will clear the UERR_FLG0 in PAR_ECC_STAT re...

Page 1595: ...eld Value Description 31 10 Reserved 0 Reads return 0 Writes have no effect 9 0 RXOVRN_BUF_ADDR 200h 3FCh Address in RXRAM at which an overwrite occurred This address value will show only the offset a...

Page 1596: ...n compare during analog loopback 0 Read No miscompares occurred on any of the eight chip select pins vs the internal chip select number CSNR during transfers Write No effect 1 Read A comparison betwee...

Page 1597: ...ites have no effect 5 3 ERR SCS PIN Inject error on chip select pin number x The value in this field is decoded as the number of the chip select pin on which to inject an error During analog loopback...

Page 1598: ...ESCALE_FMT1 Extended Prescale value for SPIFMT1 EPRESCALE_FMT1 determines the bit transfer rate of data format 1 if the SPI MibSPI is the network master EPRESCALE_FMT1 is use to derive SPICLK from VCL...

Page 1599: ...physically implemented register The clock rate for data format 0 can be calculated as BRFormat0 VCLK EPRESCALE_FMT0 1 Write This register field should be written if a SPICLK prescaler of more VCLK 25...

Page 1600: ...ESCALE_FMT3 Extended Prescale value for SPIFMT3 EPRESCALE_FMT3 determines the bit transfer rate of data format 3 if the SPI MibSPI is the network master EPRESCALE_FMT3 is use to derive SPICLK from VCL...

Page 1601: ...MT2 15 8 Read Reading this field will reflect the PRESCALE value based on the last written register field that is EXTENDED_PRESCALE2 10 0 or SPIFMT2 15 8 register Note If Extended Prescaler is require...

Page 1602: ...ble 28 58 ECC Diagnostic Status Register ECCDIAG_STAT Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads return 0 Writes have no effect 17 DEFLG 1 Double bit error flag 0 Read No er...

Page 1603: ...ng and after any of the module level resets System level resets or even Power on Reset NOTE A Read to SBERRADDR1 Register will clear the SBE_FLG1 in PAR_ECC_STAT register However in emulation mode VBU...

Page 1604: ...s The offset address of TXRAM can vary from 000h 1FFh if EXTENDED_BUF mode is disabled If the EXTENDED_BUF mode is enabled the offset address can vary from 000h 3FFh The register does not clear its co...

Page 1605: ...each for TXRAM replicating the SPIDAT1 register and RXRAM replicating the SPIBUF register The buffers can be partitioned into multiple transfer groups each containing a variable number of buffers Each...

Page 1606: ...device datasheet to identify the control bit for the multi buffer RAM This starts the initialization process The BUFINITACTIVE bit will get set to reflect that the initialization is ongoing 3 When the...

Page 1607: ...this buffer until the corresponding RXEMPTY flag is set new receive data can be stored in RXDATA without data loss 3h skip single transfer overwrite protect mode Skip this buffer until both of the co...

Page 1608: ...o the delay counter No transaction will be performed until the WDELAY counter overflows The SPICS pins will be de activated for at least WDELAY 2 VCLK_Period duration 25 24 DFSEL Data word format sele...

Page 1609: ...CS 0 0h No chip select pin is active 20h x 1h x 21h x x 2h x 22h x x 3h x x 23h x x x 4h x 24h x x 5h x x 25h x x x 6h x x 26h x x x 7h x x x 27h x x x x 8h x 28h x x 9h x x 29h x x x Ah x x 2Ah x x x...

Page 1610: ...he received data is copied into RXBUF while it is already full RXOVR is set Overruns always occur to RXBUF not to RXRAM the contents of RXRAM are overwritten only after it is read by the Peripheral VB...

Page 1611: ...r mode the desync flag is always guaranteed to be for the current buffer Note This flag is cleared to 0 when the RXDATA field of the RXRAM register is read 0 No slave desynchronization is detected 1 A...

Page 1612: ...mode the parity locations are addressable at the address between RAM_BASE_ADDR 0x400h and RAM_BASE_ADDR 0x7FFh Each location corresponds sequentially to each TXRAM word then to each RXRAM word See Fi...

Page 1613: ...ice Datasheet for the actual value of BASE Parity ECC127 Parity ECC126 RXBUF0 RXBUF1 RXBUF126 RXBUF127 0 31 Parity ECC locations are not accessible by CPU Parity ECC0 Parity ECC1 Parity ECC127 Parity...

Page 1614: ...r to specific Device Datasheet for the actual value of BASE Parity ECC255 Parity ECC254 RXBUF0 RXBUF1 RXBUF254 RXBUF255 0 31 Parity ECC locations are not accessible by CPU Parity ECC0 Parity ECC1 Pari...

Page 1615: ...h a value of A001_AA55 If the polarity of the parity is set to odd the corresponding parity location parity5 will get updated with equivalent parity of 1011 in its field During parity memory test mode...

Page 1616: ...Option MibSPIP 28 5 2 Example of ECC Memory Organization Suppose TXBUF5 6th location in TXRAM portion in the multi buffer RAM is written with a value of A001_AA55 then the corresponding ECC bits will...

Page 1617: ...of operation In each mode different configurations like Phase Polarity affect the pin timings The pin directions are based on the mode of operation Master mode SPI SPICLK SPI Clock Output SPISIMO SPI...

Page 1618: ...SPIENA VCLK Dotted vertical lines indicate the receive edges Write to SPIDAT MibSPI Pin Timing Parameters www ti com 1618 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instru...

Page 1619: ...er Write to SPIDAT SPICLK VCLK SPICLK SPISOMI SPISIMO Dotted vertical lines indicate the receive edges Write to SPIDAT www ti com MibSPI Pin Timing Parameters 1619 SPNU563A March 2018 Submit Documenta...

Page 1620: ...ster will wait for an active low from the Slave on the input pin to start the SPICLK 28 6 4 Slave Mode Timing Parameter Details In case of Slave mode the module will drive only the SPISOMI and SPIENA...

Page 1621: ...1 protocol specified in the LIN Specification Package This module can be configured to operate in either SCI UART or LIN mode NOTE This chapter describes a superset implementation of the LIN SCI modul...

Page 1622: ...he SCI module Standard universal asynchronous receiver transmitter UART communication Supports full or half duplex operation Standard nonreturn to zero NRZ format Double buffered receive and transmit...

Page 1623: ...Slave automatic synchronization Synchronization break detection Optional baud rate update Synchronization validation 231 programmable transmission rates with 7 fractional bits Wakeup on LINRX dominan...

Page 1624: ...receiver shift register SCIRXSHF shifts data in from the LINRX pin one bit at a time and transfers completed data into the receive data buffer The receiver data buffer register SCIRD contains receive...

Page 1625: ...R24 26 SCIGCR1 25 TXENA SCIFLR 10 BRKDT INT ENA WAKEUP INT ENA PE OE FE RECEIVER TRANSMITTER CLOCK Baud clock SCIBAUD generator Baud rate registers LINTX RXENA SCISETINT 9 SCISETINT 0 SCISETINT 1 SCIG...

Page 1626: ...res www ti com 1626 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Serial Communication Interface SCI Local Interconnect Network LIN Module Figure 29 2...

Page 1627: ...h receive and transmit data is in nonreturn to zero NRZ format which means that the transmit and receive lines are at logic high when idle Each frame transmission begins with a start bit in which the...

Page 1628: ...SCI baud clock periods to detect a valid start bit The bus is considered idle if this condition is not met When a valid start bit is detected the SCI determines the value of each bit by sampling the L...

Page 1629: ...d added to their Tbit If the character length is more than 10 then the modulation table will be a rolled over version of the original table Table 29 1 as shown in Table 29 2 The baud rate will vary ov...

Page 1630: ...Bit 0 Stop Bit 1 Table 29 2 Superfractional Bit Modulation for SCI Mode Maximum Configuration 1 BRS 30 28 Start Bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Addr Parity Stop0 Stop1 0h 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1631: ...bits is a data frame Figure 29 6 illustrates the format of several blocks and frames with idle line mode There are two ways to transmit an address frame using idle line mode Method 1 In software deli...

Page 1632: ...Communication Format 29 2 1 4 2 Address Bit Multiprocessor Mode In the address bit protocol each frame has an extra bit immediately following the data field called an address bit A frame with the add...

Page 1633: ...rom the SCIRXSHF register to the RDy receive buffers and TDy transmit buffers register to SCITXSHF register The 3 bit compare register contains the number of data bytes expected to be received or tran...

Page 1634: ...t Compare TX DMA Request CHECKSUM CALCULATOR TX MBUF MODE TX Ready Flag Not MBUF MODE SCI www ti com 1634 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporate...

Page 1635: ...rs SCIINTVECT0 and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders Each interrupt condition has a bit to enable disable the interrupt in the SCIS...

Page 1636: ...data to SCITD in the transmit Interrupt service routine Writing data to the SCITD register clears the TXRDY bit When this data has been moved to the SCITXSHF register the TXRDY bit is set again The in...

Page 1637: ...the end of the frame Each of these flags is located in the receiver status SCIFLR register There are 16 interrupt sources in the SCI LIN module In SCI mode 8 interrupts are supported as seen in Table...

Page 1638: ...he corresponding RDy buffer successfully If the multi buffer option is disabled then DMA requests will be generated on a byte per byte basis In multiprocessor mode the SCI can generate receiver interr...

Page 1639: ...kpoint until its current reception or transmission is complete this bit is used only in an emulation environment Set the LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver intern...

Page 1640: ...Buffer Mode Single buffer mode is selected when the MBUF MODE bit in SCIGCR1 is cleared to 0 In this mode SCI waits for data to be written to SCITD transfers it to SCITXSHF and transmits the data The...

Page 1641: ...ltiprocessor Communication When the SCI receives data and transfers that data from SCIRXSHF to SCIRD the RXRDY bit is set and if RX INT ENA is set the SCI also generates an interrupt The interrupt tri...

Page 1642: ...vice Using sleep mode can help free some CPU resources Except for the RXRDY flag the SCI continues to update the receiver status flags see Table 29 13 while sleep mode is active In this way if an erro...

Page 1643: ...ponse space and inter byte spaces In frame response and inter byte spaces may be 0 Figure 29 12 LIN Protocol Message Frame Format Master Header and Slave Response There is no arbitration in the defini...

Page 1644: ...bytes in the data fields of the response Figure 29 14 Response Format of LIN Message Frame The format of the response is a stream of N data fields and one checksum field Typically N is from 1 to 8 wi...

Page 1645: ...time Tbit The bit time is derived from the fields P and M in the baud rate selection register BRS There is an additional 3 bit fractional divider value field U in the BRS register which further fine...

Page 1646: ...1 In LIN master mode bit modulation applies to synch field identifier field response field 2 In LIN slave mode bit modulation applies to identifier field response field Table 29 7 Superfractional Bit...

Page 1647: ...its The synch break length may be extended from the minimum with the 3 bit SBREAK value in the LINCOMP register The synchronization break delimiter SDEL consists of a minimum of 1 recessive high bit t...

Page 1648: ...red frame header the master node will set the NRE flag and a NRE interrupt will occur if enabled If a collision occurs a frame error and checksum error may arise before the NRE error Those errors are...

Page 1649: ...d as required by the LIN protocol For detection of the dominant data stream of the synch break the synchronizer counter is started on a falling edge and stopped on a rising edge of the LINRX On detect...

Page 1650: ...Instruments Incorporated Serial Communication Interface SCI Local Interconnect Network LIN Module Figure 29 18 Synchronization Validation Process and Baud Rate Adjustment If the synch field is not det...

Page 1651: ...frames this communication needs to be stopped before issuing another header To stop the extended frame communication the STOP EXT FRAME bit must be set Figure 29 19 Optional Embedded Checksum in Resp...

Page 1652: ...me is not fully completed within the maximum length allowed TFRAME_MAX After this time a no response error NRE is flagged in the NRE bit of the SCIFLR register An interrupt is triggered if enabled As...

Page 1653: ...e by writing the POWERDOWN bit NOTE After the timeout was flagged a SW nRESET should be asserted before entering Low Power Mode This is required to reset the receiver in case that an incomplete frame...

Page 1654: ...he LINRX pin as shown in Figure 29 21 NOTE If BE Occurs due to New Header reception during a Slave Response NRE TIMEOUT flag will not be set for the new Frame Figure 29 21 TXRX Error Detector 29 3 1 8...

Page 1655: ...m is calculated over each byte by adding with carry where the carry bit of each addition is added to the LSB of its resulting sum For the transmitting node the checksum byte sent at the end of a messa...

Page 1656: ...received identifier and thus there will be an ID match regardless of the content of the ID SlaveTask BYTE field in the LINID register NOTE When the HGEN CTRL bit 0 the LIN nodes compare the received...

Page 1657: ...g ID TX Fla g Parity Enable ID Parity Error No ID Parity Error HGEN CTRL ID INT 0 1 0 1 From AND AND RX No ID Parity Error RXENA RX Match TX Match ID RX Flag ID TX Fla g No ID Parity Error HGEN CTRL w...

Page 1658: ...y reading the corresponding interrupt offset in the SCIINTVECT0 1 register 2 For LENGTH less than or equal to 4 Read to RD0 register will clear the RXRDY flag 3 For LENGTH greater than 4 Read to RD1 r...

Page 1659: ...29 3 3 LIN DMA Interface LIN DMA Interface uses the SCI DMA interface logic DMA requests for receive RXDMA request and transmit TXDMA request are available for the SCI LIN module There are two modes...

Page 1660: ...fields in the LINMASK register Set the SWnRST bit to 1 after LIN is configured Perform receiving or transmitting data see Section 29 3 4 1 or Section 29 3 4 2 29 3 4 1 Receiving Data The LIN receiver...

Page 1661: ...independently of the receiver The ID TX flag is set after a valid LIN ID is received with TX Match An ID interrupt is generated if enabled 29 3 4 2 1 Transmitting Data in Single Buffer Mode Single buf...

Page 1662: ...leared The BLIN module may enter low power mode either when there was no activity on the LINRX pin for more than 4s this can be either a constant recessive or dominant level or when a Sleep Command fr...

Page 1663: ...bits Figure 29 26 Wakeup Signal Generation 51 Assuming a perfect bus with no noise or loading effects a write of 0xF0 to TD0 will load the transmitter to meet the wakeup signal timing requirement for...

Page 1664: ...onditions the MBRS register must be set to assure that the LIN 2 0 real time based timings meet the LIN 1 3 bit time base A node triggering the wakeup should set the MBRS register accordingly to meet...

Page 1665: ...ed Serial Communication Interface SCI Local Interconnect Network LIN Module 29 6 GPIO Functionality The following section applies to all device pins that can be configured as functional or general pur...

Page 1666: ...rection control register SCIPIO1 Section 29 7 15 AND the open drain feature is not enabled in the SCIPIO6 register Section 29 7 20 29 6 4 Open Drain Feature Enabled on a Pin The following apply if the...

Page 1667: ...l Register Section 29 7 7 1Ch SCIFLR SCI Flags Register Section 29 7 8 20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Section 29 7 9 24h SCIINTVECT1 SCI Interrupt Vector Offset 1 Section 29 7 10 28h SC...

Page 1668: ...this register Figure 29 28 SCI Global Control Register 0 SCIGCR0 offset 00 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LEGEND R Read only R WP Read Write in privileged mode only n value after...

Page 1669: ...fective in LIN and SCI modes RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multi buffers 0 The receiver will not transfer data from the shift buffer to the receiv...

Page 1670: ...ctive in LIN mode only This bit controls the type of checksum to be used classic or enhanced 0 Classic checksum is used 1 Enhanced checksum is used 10 MBUF MODE Multi buffer mode This bit is effective...

Page 1671: ...clock is VCLK 16 1 The internal SCICLK is the clock source LIN mode 0 The node is in slave mode 1 The node is in master mode 4 STOP SCI number of stop bits per frame This bit is effective in SCI mode...

Page 1672: ...line mode is used 1 Address bit mode is used LIN mode 0 ID4 and ID5 are not used for length control 1 ID4 and ID5 are used for length control 1 The flags are frozen with their reset value while SWnRST...

Page 1673: ...ed after the checkbyte has been received and compared Checksum reception is not guaranteed if CC bit is write cleared by software during the checksum reception See Section 29 3 1 6 for more details 0...

Page 1674: ...in LIN or SCI mode When this bit is set the SCI LIN module attempts to enter local low power mode If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is...

Page 1675: ...T BE INT Set bit error interrupt This bit is effective in LIN mode only Setting this bit enables the SCI LIN module to generate an interrupt when there is a bit error 0 Read The interrupt is disabled...

Page 1676: ...rames When this bit is 1 RX DMA requests are generated for both address and data frames 0 Read The DMA request is disabled for address frames the receive interrupt request is enabled for address frame...

Page 1677: ...interrupt when a timeout occurs after one wakeup signal has been sent 0 Read The interrupt is disabled Write No effect 1 Read or write The interrupt is enabled 5 Reserved 0 Reads return 0 Writes have...

Page 1678: ...only WL Write in LIN mode only WC Write in SCI compatible mode only n value after reset Table 29 17 SCI Clear Interrupt Register SCICLEARINT Field Descriptions Bit Field Value Description 31 CLR BE IN...

Page 1679: ...hen set 0 Read The interrupt is disabled Write No effect 1 Read The interrupt is enabled Write The interrupt is disabled 23 19 Reserved 0 Reads return 0 Writes have no effect 18 CLR RX DMA ALL Clear r...

Page 1680: ...nterrupt is disabled Write No effect 1 Read The interrupt is enabled Write The interrupt is disabled 6 CLR TOAWUS INT Clear timeout after wakeup signal interrupt This bit is effective in LIN mode only...

Page 1681: ...INT LVL Set bit error interrupt level This bit is effective in LIN mode only 0 Read The interrupt level is mapped to the INT0 line Write No effect 1 Read or write The interrupt level is mapped to the...

Page 1682: ...ped to the INT1 line 12 10 Reserved 0 Reads return 0 Writes have no effect 9 SET RX INT LVL Set receiver interrupt level This bit is effective in LIN or SCI compatible mode 0 Read The interrupt level...

Page 1683: ...terconnect Network LIN Module Table 29 18 SCI Set Interrupt Level Register SCISETINTLVL Field Descriptions continued Bit Field Value Description 0 SET BRKDT INT LVL Set break detect interrupt level Th...

Page 1684: ...Description 31 CLR BE INT LVL Clear bit error interrupt This bit is effective in LIN mode only 0 Read The interrupt level is mapped to the INT0 line Write No effect 1 Read The interrupt level is mappe...

Page 1685: ...in SCI compatible mode only 0 Read The receive interrupt request for address frames is mapped to the INT0 line Write No effect 1 Read The receive interrupt request for address frames is mapped to the...

Page 1686: ...CLR TIMEOUT INT LVL Clear timeout interrupt This bit is effective in LIN mode only 0 Read The interrupt level is mapped to the INT0 line Write No effect 1 Read The interrupt level is mapped to the IN...

Page 1687: ...e Section 29 3 1 8 for more information The bit error flag is cleared by any of the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit On reception of...

Page 1688: ...bit is set when an inconsistent synch field error has been detected by the synchronizer during header reception See Section 29 3 1 5 2 for more information The inconsistent synch field error flag is...

Page 1689: ...to SCIRD overwrites unread data already in SCIRD or the RDy buffers in LINRD0 and LINRD1 Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit 1 The OE flag...

Page 1690: ...ollowing Setting the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit Reading the LINID register Receiving a new synch break Reading the corresponding interrupt offset in SCI...

Page 1691: ...the SET RX INT bit is set SCISETINT 9 RX RDY is cleared by the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit Reading the SCIRD register in compati...

Page 1692: ...Section 29 4 3 for more information 0 Read No timeout occurred after one wakeup signal 150 ms Write No effect 1 Read Timeout occurred after one wakeup signal Write The bit is cleared to 0 5 Reserved 0...

Page 1693: ...ule out of power down mode An interrupt is generated if the SET WAKEUP INT bit SCISETINT 2 is set It is cleared by the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writi...

Page 1694: ...nterrupts Note The flags for the receive SCIFLR 9 and the transmit SCIFLR 8 interrupt cannot be cleared by reading the corresponding offset vector in this register see detailed description in SCIFLR r...

Page 1695: ...ode these bits indicate the transmitter receiver format for the number of characters 1 to 8 There can be up to eight characters with eight bits each 0 The response field has 1 byte character 1h The re...

Page 1696: ...tuning of the fractional baud rate with seven more intermediate values for each of the M fractional divider values See Section 29 3 1 4 1 for more details 27 24 M 0 3h SCI LIN 4 bit fractional divide...

Page 1697: ...l except for column 2 Table 29 25 Comparative Baud Values for Different P Values Asynchronous Mode 1 2 24 Bit Register Value Baud Selected Percent Error Decimal Hex Ideal Actual 26 00001A 115200 11574...

Page 1698: ...This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag 29 7 13 2 Receiver Data Buffer SCIRD This register provides a location for...

Page 1699: ...s ready to be loaded with another byte of data Note If SET TX INT is set this data transfer also causes an interrupt NOTE Data written to the SCITD register that is fewer than eight bits long must be...

Page 1700: ...C 0 See Table 29 31 for the LINTX pin control with this bit and others 0 LINTX is a general purpose input pin 1 LINTX is a general purpose output pin 1 RX DIR Receive pin direction This bit is effecti...

Page 1701: ...R X R X R X LEGEND R Read only X value is indeterminate n value after reset Table 29 33 SCI Pin I O Control Register 2 SCIPIO2 Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reads ret...

Page 1702: ...pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output See Table 29 31 for an explanation of this bit s effect in com...

Page 1703: ...ve in LIN or SCI mode This bit sets the logic to be output on pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output...

Page 1704: ...ffect 2 TX CLR Transmit pin clear This bit is effective in LIN or SCI mode This bit clears the logic to be output on pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purp...

Page 1705: ...bles open drain capability in the output pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output 0 Open drain function...

Page 1706: ...inal Functions in the device datasheet for default pin settings Table 29 38 SCI Pin I O Control Register 7 SCIPIO7 Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reads return 0 Writes...

Page 1707: ...Read Write R Read only n value after reset Refer to the Terminal Functions in the device datasheet for default pin settings Table 29 39 SCI Pin I O Control Register 8 SCIPIO8 Field Descriptions Bit Fi...

Page 1708: ...the synch field The default value is 0 The formula to program the value in Tbits for the synchronization delimiter is TSDEL SDEL 1 Tbit 0 The synch delimiter has 1 Tbit 1h The synch delimiter has 2 T...

Page 1709: ...RXSHFT register is transferred to the corresponding RDy bit field according to the number of bytes received A read of this byte clears the RXDY byte Note RD x 1 is equivalent to data byte x of the LIN...

Page 1710: ...hat is received in the SCIRXSHFT register is transferred to the corresponding register according to the number of bytes received Note RD x 1 is equivalent to data byte x of the LIN frame 23 16 RD5 0 F...

Page 1711: ...only This 8 bit mask is used for filtering an incoming ID message and comparing it to the ID byte A compare match of the received ID with the RX ID MASK will set the ID RX flag and trigger an ID inte...

Page 1712: ...e contains the current message identifier During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID parity error and there has been an RX TX match 15...

Page 1713: ...2 Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission 7 0 TD3 0 FFh 8 Bit transmit buffer 3 Byte 3 to be transmitted is written into this register and t...

Page 1714: ...criptions Bit Field Value Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 0 MBR 0 1FFFh Maximum baud rate prescaler This bit is effective in LIN mode only This 13 bit prescaler is...

Page 1715: ...le 29 48 Input Output Error Enable Register IODFTCTRL Field Descriptions Bit Field Value Description 31 BEN Bit error enable This bit is effective in LIN mode only This bit is used to create a bit err...

Page 1716: ...TER 2h Invert the TX Pin value at TBIT_CENTER SCLK 3h Invert the TX Pin value at TBIT_CENTER 2 SCLK 18 16 TX SHIFT Transmit shift These bits define the amount by which the value on TX pin is delayed s...

Page 1717: ...8 Serial Communication Interface SCI Module This chapter contains the description of the serial communication interface SCI module Topic Page 30 1 Introduction 1718 30 2 SCI Communication Formats 1720...

Page 1718: ...CPU resources during multiprocessor communication and then wake up to receive an incoming message The 24 bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate s...

Page 1719: ...CI VCLK Peripheral www ti com Introduction 1719 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Serial Communication Interface SCI Module The SCI receiv...

Page 1720: ...transmit data is in nonreturn to zero NRZ format which means that the transmit and receive lines are at logic high when idle Each frame transmission begins with a start bit in which the transmitter p...

Page 1721: ...is being received and synchronizes itself to the bus To prevent interpreting noise as Start bit SCI expects SCIRX line to be low for at least four contiguous SCI baud clock periods to detect a valid s...

Page 1722: ...ase of data sent to an individual device the receiving devices must determine when they are being addressed When a message is not intended for them the devices can ignore the following data When only...

Page 1723: ...y a delay loop in software Method 2 can be implemented by using the transmit buffer and the TXWAKE bit in the following manner Step1 Write a 1 to the TXWAKE bit Step2 Write a dummy data value to the S...

Page 1724: ...ss bit A frame with the address bit set to 1 is an address frame a frame with the address bit set to 0 is a data frame The idle period timing is irrelevant in this mode Figure 30 5 illustrates the for...

Page 1725: ...0 and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders Each interrupt condition has a bit to enable disable the interrupt in the SCISETINT and SCI...

Page 1726: ...to SCITD in the transmit Interrupt service routine Writing data to the SCITD register clears the TXRDY bit When this data has been moved to the SCITXSHF register the TXRDY bit is set again The interr...

Page 1727: ...generated if enabled A message is valid for both the transmitter and the receiver if there is no error detected until the end of the frame Each of these flags is located in the receiver status SCIFLR...

Page 1728: ...ultiprocessor mode the SCI can generate receiver interrupts for address frames and DMA requests for data frames This is controlled by an extra select bit SET RX DMA ALL If the SET RX DMA ALL bit is se...

Page 1729: ...r is set to 1 Of particular importance is the SWnRST bit in the SCIGCR1 register The SWnRST is an active low bit initialized to 0 and keeps the SCI in a reset state until it is programmed to 1 Therefo...

Page 1730: ...0 5 2 Transmitting Data The SCI transmitter is enabled if both the TX FUNC bit and the TXENA bit are set to 1 If the TX FUNC bit is not set the SCITX pin functions as a general purpose I O pin rather...

Page 1731: ...are accessible during local power down mode as any register access enables the clock to SCI for that particular access alone The wake up interrupt is used to allow the SCI to exit low power mode auto...

Page 1732: ...k the address in SCIRD against its own address If it is still being addressed then sleep mode should remain disabled Otherwise the SLEEP bit should be set again Following is a sequence of events typic...

Page 1733: ...rrupt Level Register Section 30 7 5 18h SCICLEARINTLVL SCI Clear Interrupt Level Register Section 30 7 6 1Ch SCIFLR SCI Flags Register Section 30 7 7 20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Sect...

Page 1734: ...e this register Figure 30 8 SCI Global Control Register 0 SCIGCR0 offset 00 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LEGEND R W Read Write R Read only R WP Read Write in privileged mode onl...

Page 1735: ...previously written to SCITD is sent 24 RXENA Receive enable RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD 0 The receiver will not transfer data from the shift buffer to the rece...

Page 1736: ...rame is detected The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set regardless of the value of the SLEEP bit In this w...

Page 1737: ...the parity calculation For odd parity the SCI transmits and expects to receive a value in the parity bit that makes odd the total number of bits in the frame with the value of 1 For even parity the S...

Page 1738: ...OE INT Set overrun error interrupt Setting this bit enables the SCI module to generate an interrupt when an overrun error occurs 0 Read The interrupt is disabled Write No effect 1 Read or write The i...

Page 1739: ...is disabled Write No effect 1 Read or write The interrupt is enabled 8 SET TX INT Set transmitter interrupt Setting this bit enables the SCI to generate a transmit interrupt as data is being transferr...

Page 1740: ...ar framing error interrupt This bit disables the framing error interrupt when set 0 Read The interrupt is disabled Write No effect 1 Read The interrupt is enabled Write The interrupt is disabled 25 CL...

Page 1741: ...r is disabled 15 10 Reserved 0 Reads return 0 Writes have no effect 9 CLR RX INT Clear receiver interrupt This bit disables the receiver interrupt when set 0 Read The interrupt is disabled Write No ef...

Page 1742: ...0 Writes have no effect 26 SET FE INT LVL Set framing error interrupt level 0 Read The interrupt level is mapped to the INT0 line Write No effect 1 Read or write The interrupt level is mapped to the I...

Page 1743: ...line Write No effect 1 Read or write The interrupt level is mapped to the INT1 line 30 7 6 SCI Clear Interrupt Level Register SCICLEARINTLVL Figure 30 13 and Table 30 9 illustrate this register Figur...

Page 1744: ...The receive interrupt request for address frames is mapped to the INT1 line Write The receive interrupt request for address frames is mapped to the INT0 line 17 10 Reserved 0 Reads return 0 Writes ha...

Page 1745: ...ramed Detection of a framing error causes the SCI LIN to generate an error interrupt if the SET FE INT bit SCISETINT 26 The framing error flag is cleared by the following Setting of the SWnRST bit Set...

Page 1746: ...eads return 0 Writes have no effect 12 RXWAKE Receiver wakeup detect flag The SCI sets this bit to indicate that the data currently in SCIRD is an address RXWAKE is cleared by the following Setting of...

Page 1747: ...ot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0 1 register 3 The transmit interrupt request can be eliminated until the next series of data written into the transmit buf...

Page 1748: ...is bit is set when the SCI detects a break condition on the LINRX pin A break condition occurs when the SCIRX pin remains continuously low for at least 10 bits after a missing first stop bit that is a...

Page 1749: ...e flags for the receive SCIFLR 9 and the transmit SCIFLR 8 interrupt cannot be cleared by reading the corresponding offset vector in this register see detailed description in SCIFLR register 30 7 9 SC...

Page 1750: ...escription 31 3 Reserved 0 Reads return 0 Writes have no effect 2 0 CHAR Character length control bits These bits set the SCI character length from 1 to 8 bits When data of fewer than eight bits in le...

Page 1751: ...0 Reads return 0 Writes have no effect 23 0 BAUD 0 FF FFFFh SCI 24 bit baud selection The SCI has an internally generated serial clock determined by the VCLK and the prescalers BAUD in this register...

Page 1752: ...continually read the data buffer without affecting the RXRDY flag 30 7 12 2 Receiver Data Buffer SCIRD This register provides a location for the receiver data Figure 30 20 and Table 30 19 illustrate...

Page 1753: ...ready to be loaded with another byte of data Note If SET TX INT bit SCISETINT 8 is set this data transfer also causes an interrupt NOTE Data written to the SCITD register that is fewer than eight bit...

Page 1754: ...23 for the SCITX pin control with this bit and others 0 SCITX is a general purpose input pin 1 SCITX is a general purpose output pin 1 RX DIR Receive pin direction This bit determines the data directi...

Page 1755: ...TX IN RX IN Reserved R 0 R X R X R X LEGEND R Read only n value after reset X value is indeterminate Table 30 25 SCI Pin I O Control Register 2 SCIPIO2 Field Descriptions Bit Field Value Description 3...

Page 1756: ...following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output See Table 30 23 for an explanation of this bit s effect in combination with oth...

Page 1757: ...nsmit pin set This bit sets the logic to be output on pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output See Tabl...

Page 1758: ...Reads return 0 Writes have no effect 2 TX CLR Transmit pin clear This bit clears the logic to be output on pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O T...

Page 1759: ...drain capability in the output pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output 0 Open drain functionality is d...

Page 1760: ...in is disabled 1 RX PD Receive pin pull control disable This bit disables pull control capability on the input pin SCIRX 0 Pull control on the SCIRX pin is enabled 1 Pull control on the SCIRX pin is d...

Page 1761: ...e Register IODFTCTRL Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reads return 0 Writes have no effect 26 FEN Frame error enable This bit is used to create a frame error 0 No error...

Page 1762: ...12 Reserved 0 Reads return 0 Writes have no effect 11 8 IODFTENA IODFT enable key Write access permitted in Privilege mode only Ah IODFT is enabled All Others IODFT is disabled 7 2 Reserved 0 Reads re...

Page 1763: ...ments Incorporated Serial Communication Interface SCI Module 30 8 GPIO Functionality The following sections apply to all device pins that can be configured as functional or general purpose I O pins 30...

Page 1764: ...n as an output pin if the TX DIR bit is set in the pin direction control register SCIPIO1 Section 30 7 14 AND the open drain feature is not enabled in the SCIPIO6 register Section 30 7 19 30 8 4 Open...

Page 1765: ...master communication module providing an interface between the Texas Instruments TI microcontroller and devices compliant with Philips Semiconductor I2 C bus specification version 2 1 and connected by...

Page 1766: ...nable disable capability Seven interrupts that can be used by the CPU Operates with VBUS frequency from 6 7 MHz up Operates with module frequency between 6 7 MHz to 13 3 MHz Module enable disable capa...

Page 1767: ...compliant I2C devices that are incapable of generating an ACK The I2C module consists of the following primary blocks A serial Interface one data pin SDA and one clock pin SCL The device register inte...

Page 1768: ...C I2CDSET I2CDCLR I2CPDR I2CPDIS I2CSRS SDA I2CEMDR Filter Noise Filter Clock synchronizer I2CPDIR I2CPDR I2CPDIS I2CSRS I2CPFNC I2CDOUT I2CDSET I2CDCLR TX DMA REQ I2CDMACR RX DMA REQ I2CSTR I2CPSEL I...

Page 1769: ...frequency at which the I2C module operates A programmable prescaler in the I2C module divides down the input clock to produce the module clock To specify the divide down value initialize the I2CPSC f...

Page 1770: ...is generated by the master device for each data bit transferred Because of a variety of different technology devices that can be connected to the I2C bus the levels of logic 0 low and logic 1 high ar...

Page 1771: ...I2CMDR must both be set to 1 For the I2C module to end a data transfer with a STOP condition the STOP condition bit STP must be set to 1 When the BB bit is set to 1 and the STT bit is set to 1 a repe...

Page 1772: ...anded address enable XA bit of I2CMDR and make sure the free data format mode is off FDF 0 in I2CMDR Figure 31 7 I2C Module 7 Bit Addressing Format 31 2 5 2 10 Bit Addressing Format The 10 bit address...

Page 1773: ...nore any new bits the I2C module must send a no acknowledge NACK bit during the acknowledge cycle on the bus Table 31 1 summarizes the various ways a NACK can be generated Table 31 1 Ways to Generate...

Page 1774: ...k pulses are inhibited and the SCL is held low when the intervention of the device is required RSFULL 1 after a byte has been received At the end of the transfer the master receiver signals the end of...

Page 1775: ...free run mode when the FREE bit I2CMDR 14 is set to 1 This bit is primarily used on an emulator when encountering a breakpoint while debugging software When the FREE bit is set to 0 the I2C responds d...

Page 1776: ...rocedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that loses the arbitration switches to the slave receiver mode sets the...

Page 1777: ...ines the length of the low period and the fastest device determines the length of the high period If a device pulls down the clock line for a longer time the result is that all clock generators must e...

Page 1778: ...2C registers are ready to be accessed RXRDY Receive data ready interrupt Generated when the received data in the receive shift register I2CSR has been copied into the data receive register I2CDRR The...

Page 1779: ...nt occurs soon after the start condition but before the first bit of the address is transmitted In this event no DMA activity should be initiated without the slave ACK being received 31 5 3 I2C Enable...

Page 1780: ...ctive pull down function by writing to the corresponding bit in I2CPSEL register The pull up pull down function is active on the pin only when the pull enabled is programmed in the I2CPDIS register Th...

Page 1781: ...Receive Register Section 31 6 7 1Ch I2CSAR I2C Slave Address Register Section 31 6 8 20h I2CDXR I2C Data Transmit Register Section 31 6 9 24h I2CMDR I2C Mode Register Section 31 6 10 28h I2CIVR I2C In...

Page 1782: ...r I2COAR Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reads return 0 Writes have no effect 9 0 OA 0 3FFh Own address These bits reflect the bus address of the I2C module When the ex...

Page 1783: ...Register I2CIMR Field Descriptions Bit Field Value Description 15 7 Reserved 0 Reads return 0 Writes have no effect 6 AASEN Address As Slave Interrupt Enable 0 AASEN interrupt is disabled 1 AASEN int...

Page 1784: ...ge sent This bit is set to 1 to indicate that a no acknowledgement NACK has been sent because the NACKMOD bit was set to 1 Writing a 1 to this bit will clear it 0 A NACK has not been sent 1 A NACK was...

Page 1785: ...general call was detected 1 An address of all zeros general call was detected 7 6 Reserved 0 Reads return 0 Writes have no effect 5 SCD Stop condition detect interrupt flag This bit is set to 1 when...

Page 1786: ...s are not ready to be accessed 1 Nonrepeat mode RM 0 ICCNT passes 0 if STP bit has not been set Repeat mode RM 1 The end of each byte was transmitted from I2CDXR 1 NACK No acknowledgement interrupt Th...

Page 1787: ...te the low time portion of the master clock signal that will appear on the SCL pin 66 where d is the value that depends on the I2CPSC see Section 31 1 3 This register must be configured while the I2C...

Page 1788: ...escriptions Bit Field Value Description 15 0 CNT Data counter This down counter is used to generate a stop condition if a stop condition is specified STP 1 Note ICCNT is a don t care when RM is set to...

Page 1789: ...9 0 SA 7 or 10 bit programmable slave address In either mode all 10 bits are readable and writable Bits 7 8 and 9 should only be used in 10 bit address mode Table 31 13 illustrates the correct mode f...

Page 1790: ...SCL becomes low and then stops If the I2C is a slave it will stop when the transmission reception completes 1 The I2C runs free 13 STT Start condition The start condition bit works with the STP bit ma...

Page 1791: ...smitter mode 0 Digital loop back mode is disabled 1 Digital loop back mode is enabled In digital loop back mode data transmitted out of the I2CDXR will be received in the I2CDRR The address of the I2C...

Page 1792: ...Activities 1 Mode 0 0 0 Idle None N A 0 0 1 Stop P N A 0 1 0 Repeat Start S A D n D Repeat n 0 1 1 Repeat Start Stop S A D n D P Repeat n 1 0 0 Idle None N A 1 0 1 Stop P N A 1 1 0 Repeat Start S A D...

Page 1793: ...there is more than one interrupt pending reading I2CIVR provides the vector for the highest priority interrupt that is pending Reading the I2CIVR will clear the corresponding flags in I2CSTR for AL N...

Page 1794: ...t and the I2C needs more data to transmit This behavior causes an extra TXRDY interrupt to be generated because the I2C recognizes the end of transfer after generating an interrupt for the next byte o...

Page 1795: ...iptions Bit Field Value Description 15 8 CLASS 0 FFh Peripheral class These bits identify the class of peripheral 7 0 REVISION 0 FFh Revision level of the I2C These bits identify the revision level of...

Page 1796: ...it event is disabled Writing a 1 to this bit will send a TXDMA request to the DMA module if PINFUNC is also cleared to 0 0 The transmit DMA is disabled 1 The transmit DMA is enabled 0 RXDMAEN Receive...

Page 1797: ...ect 1 SDADIR SDA pin direction This bit controls the direction of the I2C SDA pin when configured as a GPIO 0 SDA pin functions as an input 1 SDA pin functions as an output 0 SCLDIR SCL pin direction...

Page 1798: ...SCLOUT SCL data output This function is only active if the SCL pin is configured as an I O pin with PINFUNC 1 This bit contains the value sent to the SCL pin 0 The pin is driven low 1 The pin is driv...

Page 1799: ...clear the SCL GPIO pin 0 Read Reads return value of SCLOUT Write No effect 1 Read Reads return value of SCLOUT Write SCLOUT is cleared to logic low 0 31 6 23 I2C Pin Open Drain Register I2CPDR Figure...

Page 1800: ...DA pull disable 0 The pull function is enabled 1 The pull function is disabled 0 SCLPDIS SCL pull disable 0 The pull function is enabled 1 The pull function is disabled 31 6 25 I2C Pull Select Registe...

Page 1801: ...X Enabled Disabled Enabled No 0 0 0 Pull down Disabled Enabled No 0 0 1 Pull up Disabled Enabled No 0 1 0 Disabled Disabled Enabled No 0 1 1 Disabled Disabled Enabled No 1 X X Disabled Enabled Enable...

Page 1802: ...2018 Texas Instruments Incorporated Inter Integrated Circuit I2C Module 31 7 Sample Waveforms Figure 31 40 provides waveforms to illustrate the difference between normal operation and backward compati...

Page 1803: ...SPNU563A March 2018 EMAC MDIO Module This chapter describes the Ethernet Media Access Controller EMAC and physical layer PHY device Management Data Input Output MDIO module Topic Page 32 1 Introducti...

Page 1804: ...col 32 1 2 Features The EMAC MDIO has the following features Synchronous 10 100 Mbps operation Standard Media Independent Interface MII and or Reduced Media Independent Interface RMII to physical laye...

Page 1805: ...nfigure required parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core proce...

Page 1806: ...plication software or driver must control the divide down value The transmit and receive clock sources are provided by the external PHY to the MII_TXCLK and MII_RXCLK pins or to the RMII reference clo...

Page 1807: ...this bit Please refer to the I O Multiplexing and Control Module IOMM chapter for more details on the procedure to configure the PINMMR registers Each of the EMAC and MDIO signals for the MII and RMI...

Page 1808: ...I_RXER signals are tied to this clock The clock is generated by the PHY and is 2 5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation MII_RXD 3 0 I Receive data MII_RXD The receive data pins ar...

Page 1809: ...ynchronous to RMII_MHZ_50_CLK RMII_MHZ_50_CLK I RMII reference clock RMII_MHZ_50_CLK The reference clock is used to synchronize all RMII signals RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz...

Page 1810: ...MAC MDIO Signal MDIO_CLK PINMMR21 31 24 0b00000100 MDIO_D PINMMR23 7 0 0b00000100 Table 32 4 MII RMII Multiplexing Control MII RMII Signal Name Control for Selecting MII Signal Control for Selecting R...

Page 1811: ...he Ethernet MAC address of the EMAC port for which the frame is intended It may be an individual or multicast including broadcast address When the destination EMAC port receives an Ethernet frame with...

Page 1812: ...sence of signal energy coming from other ports If the port transmits the entire frame without detecting signal energy from other Ethernet devices the port is done with the frame 4 If the port detects...

Page 1813: ...inter The buffer pointer refers to the actual memory buffer that contains packet data during transmit operations or is an empty buffer ready to receive packet data during receive operations 2 Buffer O...

Page 1814: ...EMAC descriptor queue for the first time the software application simply writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descri...

Page 1815: ...ET YES SET SOFTWARE TX QUEUE ACTIVE TX PACKET S ADDED WRITE TX QUEUE HEAD DESCRIPTOR POINTER NO NO www ti com Architecture 1815 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas I...

Page 1816: ...OWNERSHIP BIT CLEAR CURRENT BD EOQ BIT GET NEW NOW CURRENT BD ADDRESS CLEAR CURRENT BD EOP BIT YES ZERO CURRENT BD NEXT DESC POINTER TX PACKET COMPLETE WRITE CURRENT BD NEXT DESC POINTER SET CURRENT...

Page 1817: ...TX QUEUE ACTIVE WRITE NEXT DESC POINTER VALUE TO QUEUE HEAD DESC POINTER MISQUEUED PACKET NO PROCESS MORE PACKET S RECLAIM BUFFER DESCRIPTOR BD NO YES NO RECLAIM BUFFER DESCRIPTOR BD www ti com Archit...

Page 1818: ...nterrupts are enabled by setting the mask registers RXINTMASKSET and TXINTMASKSET 2 Global interrupts are set in the EMAC control module C0RXEN and C0TXEN 3 The VIM is configured to accept C0_RX_PULSE...

Page 1819: ...smit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next des...

Page 1820: ...dicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer The software application must set this value prior to adding the...

Page 1821: ...flag is set and there are no more descriptors in the transmit list next descriptor pointer is NULL The software application can use this bit to detect when the EMAC transmitter for the corresponding...

Page 1822: ...list This pointer is not altered by the EMAC The value of pNext should never be altered once the descriptor is in an active receive queue unless its current value is NULL If the pNext pointer is initi...

Page 1823: ...r Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in...

Page 1824: ...r to a receive queue Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register When the offset register is set to a nonzero value the received packet is written to the...

Page 1825: ...ag set This flag is initially cleared by the software application before adding the descriptor to the receive queue This bit is set by the EMAC on EOP descriptors 32 2 6 5 8 Ownership OWNER Flag When...

Page 1826: ...s not discarded because the RXCSFEN bit was set in the RXMBPENABLE 32 2 6 5 16 Control Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame an...

Page 1827: ...net packet data are protected by the EMAC s internal FIFOs A descriptor is a 16 byte memory structure that holds information about a single Ethernet packet buffer which may contain a full or partial E...

Page 1828: ...IO addresses in order to enumerate all PHY devices in the system Once a PHY device has been detected the MDIO module reads the MDIO PHY link status register LINK to monitor the PHY link state Link cha...

Page 1829: ...r address has responded and whether or not the PHY currently has a link Using this information allows the software application to quickly determine which MDIO address the PHY is using 32 2 8 1 3 Activ...

Page 1830: ...tus register ALIVE and MDIO PHY link status register LINK The corresponding bit for the connected PHY 0 31 is set in ALIVE if the PHY responded to the read request The corresponding bit is set in LINK...

Page 1831: ...PHY register you want to write 3 The write operation to the PHY is scheduled and completed by the MDIO module Completion of the write operation can be determined by polling the GO bit in USERACCESSn...

Page 1832: ...Example 32 3 USERACCESS0 is assumed Note that this implementation does not check the ACK bit in USERACCESSn on PHY register reads does not follow the procedure outlined in Section 32 2 8 2 3 Since the...

Page 1833: ...face between the EMAC module and the system core is provided through the EMAC control module The EMAC consists of the following logical components The receive path includes receive DMA engine receive...

Page 1834: ...for both transmit and receive channels 32 2 9 1 9 EMAC Interrupt Controller The interrupt controller contains the interrupt related registers and logic The 26 raw EMAC interrupts are input to this su...

Page 1835: ...their associated memory buffer Thus it is possible to delay servicing of the EMAC interrupt if there are real time tasks to perform Eight channels are supplied for both transmit and receive operation...

Page 1836: ...ve flow control does not depend on the value of the incoming frame destination address A collision is generated for any incoming packet regardless of the destination address if any EMAC enabled channe...

Page 1837: ...outgoing CRC 32 2 10 2 3 Adaptive Performance Optimization APO The EMAC incorporates adaptive performance optimization APO logic that may be enabled by setting the TXPACE bit in the MAC control regis...

Page 1838: ...w pause time value is 0 then the transmit pause timer immediately expires else The EMAC transmit pause timer immediately is set to the new pause frame pause time value Any remaining pause time from th...

Page 1839: ...determine whether the given channel is enabled when set to 1 to receive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuou...

Page 1840: ...dcast promiscuous channel enable register RXMBPENABLE 32 2 11 5 Host Free Buffer Tracking The host must track free buffers for each enabled channel including unicast multicast broadcast and promiscuou...

Page 1841: ...RC bytes If the frame length is 1520 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last two bytes are the first two CRC bytes If the frame length is 1521 there a...

Page 1842: ...roper oversize jabber code align CRC data and control frames transferred to promiscuous channel No undersized frames are transferred 0 1 1 1 1 All nonaddress matching frames with and without errors tr...

Page 1843: ...is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment T...

Page 1844: ...trol register TXCONTROL Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations 32 2 12 2 Transmit Channel Teardown The host commands a transmit channel tear...

Page 1845: ...fer descriptor reads for the cell data Latency to system s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level L...

Page 1846: ...lity of the software to verify that there are no pending frames to be transferred After writing a 1 to the SOFTRESET bit it may be polled to determine if the reset has occurred If a 1 is read the rese...

Page 1847: ...t is mapped to a CPU interrupt general masking and unmasking of interrupts to control reentrancy should be done at the chip level by manipulating the interrupt core enable mask registers 32 2 16 3 MDI...

Page 1848: ...annel n free buffer count registers RXnFREEBUFFER receive channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH 7 Most devi...

Page 1849: ...e s associated transmit completion pointer in the transmit DMA state RAM The data written by the host buffer descriptor address of the last processed buffer is compared to the data in the register wri...

Page 1850: ...y acknowledge interrupts for every packet The application software must acknowledge the EMAC control module after processing packets by writing the appropriate C0TX key to the EMAC End Of Interrupt Ve...

Page 1851: ...hreshold logic as does flow control but the interrupts are independently enabled from flow control The threshold interrupts are intended to give the host an indication that resources are running low f...

Page 1852: ...edge or pulse triggered signal the application software must make use of the interrupt control logic contained in the EMAC control module Section 32 2 7 2 discusses the interrupt control contained in...

Page 1853: ...chnical Reference Manual to identify the causes of a system reset Upon a system reset the registers are reset to their default value When powering up after a system reset all the EMAC submodules need...

Page 1854: ...le Receive Threshold Interrupt Enable Register Section 32 3 4 14h C0RXEN EMAC Control Module Receive Interrupt Enable Register Section 32 3 5 18h C0TXEN EMAC Control Module Transmit Interrupt Enable R...

Page 1855: ...fies the EMAC Control Module revision 4EC8 0100h Current revision of the EMAC Control Module 32 3 2 EMAC Control Module Software Reset Register SOFTRESET The EMAC Control Module Software Reset Registe...

Page 1856: ...0 23 18 17 16 Reserved C0TXPACEEN C0RXPACEEN R 0 R W 0 R W 0 15 12 11 0 Reserved INTPRESCALE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 32 13 EMAC Control Module Interrupt...

Page 1857: ...THRESHPULSE interrupt generation for RX Channel 6 0 C0RXTHRESHPULSE generation is disabled for RX Channel 6 1 C0RXTHRESHPULSE generation is enabled for RX Channel 6 5 RXCH5THRESHEN Enable C0RXTHRESHPU...

Page 1858: ...e C0RXPULSE interrupt generation for RX Channel 6 0 C0RXPULSE generation is disabled for RX Channel 6 1 C0RXPULSE generation is enabled for RX Channel 6 5 RXCH5EN Enable C0RXPULSE interrupt generation...

Page 1859: ...ble C0TXPULSE interrupt generation for TX Channel 6 0 C0TXPULSE generation is disabled for TX Channel 6 1 C0TXPULSE generation is enabled for TX Channel 6 5 TXCH5EN Enable C0TXPULSE interrupt generati...

Page 1860: ...erved 3 STATPENDEN Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated 0 C0MISCPULSE generation is disabled for EMAC STATPEND interrupts 1 C0MISCPULSE generation is e...

Page 1861: ...conditions to generate a C0RXTHRESHPULSE interrupt 5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register 0 RX Channel 5 does not satisfy conditions to generate a C0RX...

Page 1862: ...ions to generate a C0RXPULSE interrupt 5 RXCH5STAT Interrupt status for RX Channel 5 masked by the C0RXEN register 0 RX Channel 5 does not satisfy conditions to generate a C0RXPULSE interrupt 1 RX Cha...

Page 1863: ...ditions to generate a C0TXPULSE interrupt 5 TXCH5STAT Interrupt status for TX Channel 5 masked by the C0TXEN register 0 TX Channel 5 does not satisfy conditions to generate a C0TXPULSE interrupt 1 TX...

Page 1864: ...eserved 3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the C0MISCEN register 0 EMAC STATPEND does not satisfy conditions to generate a C0MISCPULSE interrupt 1 EMAC STATPEND satisfies cond...

Page 1865: ...lue Description 31 6 Reserved 0 Reserved 5 0 RXIMAX 2 3Fh RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when C0RXPACEEN is enabled in INTCONTROL The pacing mechanism c...

Page 1866: ...Value Description 31 6 Reserved 0 Reserved 5 0 TXIMAX 2 3Fh TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when C0TXPACEEN is enabled in INTCONTROL The pacing mechanism...

Page 1867: ...terrupt Unmasked Register Section 32 4 7 24h USERINTMASKED MDIO User Command Complete Interrupt Masked Register Section 32 4 8 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register...

Page 1868: ...MDIO state machine 1 Enable the MDIO state machine 29 Reserved 0 Reserved 28 24 HIGHEST_USER_CHANNEL 0 1Fh Highest user channel that is available in the module It is currently set to 1 This implies t...

Page 1869: ...of the presence or not of a PHY with the corresponding address Writing a 1 to any bit will clear it writing a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the...

Page 1870: ...t Field Value Description 31 2 Reserved 0 Reserved 1 USERPHY1 MDIO Link change event raw value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK regis...

Page 1871: ...e When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 and the corresponding LINKINTENB bit was...

Page 1872: ...gister USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO User command complete event bit When asserted the bit indicates that the previously schedul...

Page 1873: ...ved 1 USERACCESS1 Masked value of MDIO User command complete interrupt When asserted The bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS1 registe...

Page 1874: ...erved 0 Reserved 1 USERACCESS1 MDIO user interrupt mask set for USERINTMASKED 1 Setting a bit to 1 will enable MDIO user command complete interrupts for the USERACCESS1 register MDIO user interrupt fo...

Page 1875: ...er USERINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user command complete interrupt mask clear for USERINTMASKED 1 Setting the bit to 1 will...

Page 1876: ...n it is convenient for it to do so this is not an instantaneous process Writing a 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear w...

Page 1877: ...r 0 USERPHYSEL0 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determin...

Page 1878: ...n it is convenient for it to do so this is not an instantaneous process Writing 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear whe...

Page 1879: ...Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state m...

Page 1880: ...Interrupt Mask Clear Register Section 32 5 20 100h RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register Section 32 5 21 104h RXUNICASTSET Receive Unicast Enable Set Register Se...

Page 1881: ...HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 32 5 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 32 5 46 620h RX0HDP Receive Channel 0 DMA Head D...

Page 1882: ...ansmit Frames Register Section 32 5 50 16 240h TXPAUSEFRAMES Pause Transmit Frames Register Section 32 5 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 32 5 50 18 248h TXCOLLISION Tra...

Page 1883: ...ision ID Register TXREVID Field Descriptions Bit Field Value Description 31 0 TXREV Transmit module revision 4EC0 020Dh Current transmit revision value 32 5 2 Transmit Control Register TXCONTROL The t...

Page 1884: ...he transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h Teardown transmit cha...

Page 1885: ...ceive Teardown Register RXTEARDOWN The receive teardown register RXTEARDOWN is shown in Figure 32 47 and described in Table 32 45 Figure 32 47 Receive Teardown Register RXTEARDOWN offset 18h 31 16 Res...

Page 1886: ...5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 32 46 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descript...

Page 1887: ...0 7 6 5 4 3 2 1 0 TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 32 47 Transmit Interrupt Status Masked R...

Page 1888: ...ions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel...

Page 1889: ...ns Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel...

Page 1890: ...y n value after reset Table 32 50 MAC Input Vector Register MACINVECTOR Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reserved 27 STATPEND 0 1 EMAC module statistics interrupt STATPE...

Page 1891: ...AC End Of Interrupt Vector Register MACEOIVECTOR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 INTVECT Acknowledge EMAC control module interrupts 0h Acknowledge C0RXTHRES...

Page 1892: ...ield Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND raw interrupt read before mask 14 RX6THRESHPEND 0 1 RX6THRESHPEND raw interrupt read before m...

Page 1893: ...set Table 32 53 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND masked interrupt re...

Page 1894: ...threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 11 R...

Page 1895: ...d mask clear bit Write 1 to disable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 11 RX3T...

Page 1896: ...Reserved 0 Reserved 1 HOSTPEND 0 1 Host pending interrupt HOSTPEND raw interrupt read before mask 0 STATPEND 0 1 Statistics pending interrupt STATPEND raw interrupt read before mask 32 5 18 MAC Inter...

Page 1897: ...bit Write 1 to enable interrupt a write of 0 has no effect 0 STATMASK 0 1 Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 32 5 20 MAC Interrupt Mask Clear Reg...

Page 1898: ...e buffer descriptor packet length 29 RXQOSEN Receive quality of service enable bit 0 Receive QOS is disabled 1 Receive QOS is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can...

Page 1899: ...ect channel 1 to receive promiscuous frames 2h Select channel 2 to receive promiscuous frames 3h Select channel 3 to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Sel...

Page 1900: ...1EN RXCH0EN R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 LEGEND R W Read Write R Read only W1S Write 1 to set writing a 0 has no effect n value after reset Table 32 61 Receive Unica...

Page 1901: ...no effect 4 RXCH4EN 0 1 Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN 0 1 Receive channel 3 unicast enable clear bit Write 1 to clear the...

Page 1902: ...bytes at the beginning of the data and that valid data begins on the first byte of the buffer A value of Fh 15 indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that v...

Page 1903: ...egister RXnFREEBUFFER is shown in Figure 32 69 and described in Table 32 67 Figure 32 69 Receive Channel n Free Buffer Count Register RXnFREEBUFFER offset 140h 15Ch 31 16 Reserved R 0 15 0 RXnFREEBUF...

Page 1904: ...word 1 Block all EMAC DMA controller writes to the receive buffer descriptor offset buffer length words during packet processing When this bit is set the EMAC will never write the third word to any re...

Page 1905: ...ess of this bit setting The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory 0 Transmit flow control is disabled Full duplex mode incoming pause frames are not...

Page 1906: ...A related host errors The host should read this field after a host error interrupt HOSTPEND to determine the error Host error interrupts require hardware reset in order to recover A 0 packet length is...

Page 1907: ...channel 3 4h The host error occurred on receive channel 4 5h The host error occurred on receive channel 5 6h The host error occurred on receive channel 6 7h The host error occurred on receive channel...

Page 1908: ...onjunction with SOFT bit to determine the emulation suspend mode 0 Free running mode is disabled During emulation halt SOFT bit determines operation of EMAC 1 Free running mode is enabled During emula...

Page 1909: ...in the receive FIFO 15 8 ADDRESSTYPE 2h Address type 7 0 MACCFIG 2h MAC configuration value 32 5 34 Soft Reset Register SOFTRESET The soft reset register SOFTRESET is shown in Figure 32 75 and descri...

Page 1910: ...RCADDR0 0 FFh MAC source address lower 8 0 bits byte 0 7 0 MACSRCADDR1 0 FFh MAC source address bits 15 8 byte 1 32 5 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source address high...

Page 1911: ...into a 64 bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 32 78 and de...

Page 1912: ...o be observed for test purposes This field is loaded automatically according to the backoff algorithm and is decremented by 1 for each slot time after the collision 32 5 40 Transmit Pacing Algorithm T...

Page 1913: ...outgoing pause frame with pause time of FFFFh The receive pause timer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and the...

Page 1914: ...Bytes Register MACADDRLO Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 VALID Address valid bit This bit should be cleared to 0 for unused address channels 0 Address is n...

Page 1915: ...e address bits 47 40 byte 5 Bit 40 is the group bit It is forced to 0 and read as 0 Therefore only unicast addresses are represented in the address table 32 5 45 MAC Index Register MACINDEX The MAC in...

Page 1916: ...in the queue for the selected channel Writing to these locations when they are nonzero is an error except at reset Host software must initialize these locations to 0 on reset 32 5 47 Receive Channel...

Page 1917: ...uffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be deasserted 32 5 49 Receive Channe...

Page 1918: ...te to decrement n value after reset 32 5 50 1 Good Receive Frames Register RXGOODFRAMES offset 200h The total number of good frames received on the EMAC A good frame is defined as having all of the fo...

Page 1919: ...ue to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no alignment or code error Had a CRC error A CRC error is defined as having all of the following A frame containing an even numb...

Page 1920: ...on the EMAC An undersized frame is defined as having all of the following Was any data frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was less than 64...

Page 1921: ...tion channel flow control threshold register RXnFLOWTHRESH value was greater than or equal to the channel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN...

Page 1922: ...mes are only transmitted in full duplex mode carrier loss and collisions have no effect on this statistic Transmitted pause frames are always 64 byte multicast frames so appear in the multicast transm...

Page 1923: ...f frames when transmission was abandoned due to excessive collisions Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or mult...

Page 1924: ...Did not experience late collisions excessive collisions underrun or carrier sense error Was exactly 64 bytes long If the frame was being transmitted and experienced carrier loss that resulted in a fra...

Page 1925: ...EN Octet Frames Register FRAME1024TUP offset 27Ch The total number of 1024 byte to RXMAXLEN byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any...

Page 1926: ...run frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of any size including...

Page 1927: ...anced Capture eCAP Module The enhanced Capture eCAP module is essential in systems where accurate timing of external events is important This microcontroller implements 6 instances of the eCAP module...

Page 1928: ...to four event time stamps Continuous mode capture of time stamps in a four deep circular buffer Absolute time stamp capture Difference Delta mode time stamp capture All above resources dedicated to a...

Page 1929: ...rator with 32 bit capabilities when it is not being used for input captures The counter operates in count up mode providing a time base for asymmetrical pulse width modulation PWM waveforms The CAP1 a...

Page 1930: ...2 SYNCI_EN SYNCOSEL SWSYNC ECCTL2 CAP APWM Edge Polarity Select ECCTL1 CAPxPOL ECCTL1 EVTPS ECCTL1 CAPLDEN CTRRSTx ECCTL2 RE ARM CONT ONESHT STOP_WRAP Registers ECEINT ECFLG ECCLR ECFRC Basic Operatio...

Page 1931: ...3 Event Prescale Control A When a prescale value of 1 is chosen ECCTL1 13 9 0 0 0 0 0 the input capture signal by passes the prescale logic completely Figure 33 4 Prescale Function Waveforms 33 2 2 2...

Page 1932: ...e control Once armed the eCAP module waits for 1 4 defined by stop value capture events before freezing both the Mod4 counter and contents of CAP1 4 registers time stamps Re arming prepares the eCAP m...

Page 1933: ...operation 33 2 2 6 Interrupt Control An Interrupt can be generated on capture events CEVT1 CEVT4 CTROVF or APWM events CTR PRD CTR CMP A counter overflow event FFFFFFFF 00000000 is also provided as an...

Page 1934: ...n Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Capture eCAP Module Note The CEVT1 CEVT2 CEVT3 CEVT4 flags are only active in capture mode ECCTL2 CAP_APWM 0 The CTR_PRD and CTR_CMP f...

Page 1935: ...ulates immediate mode Writing to the shadow registers CAP3 CAP4 will invoke the shadow mode During initialization you must write to the active registers for both period and compare This automatically...

Page 1936: ...G 0x1 CTRRSTx bits define EC_ABS_MODE 0x0 define EC_DELTA_MODE 0x1 PRESCALE bits define EC_BYPASS 0x0 define EC_DIV1 0x0 define EC_DIV2 0x1 define EC_DIV4 0x2 define EC_DIV6 0x3 define EC_DIV8 0x4 def...

Page 1937: ...CTR counts up without resetting and capture events are qualified on the rising edge only this gives period and frequency information On an event the TSCTR contents time stamp is first captured then Mo...

Page 1938: ...2 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_ABS_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECap1Regs ECCTL2 bit CAP_AP...

Page 1939: ...exas Instruments Incorporated Enhanced Capture eCAP Module 33 3 2 Example 2 Absolute Time Stamp Operation Rising and Falling Edge Trigger In Figure 33 10 the eCAP operating mode is almost the same as...

Page 1940: ...bit CTRRST2 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_ABS_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECap1Regs ECCTL2...

Page 1941: ...counts up without resetting and Mod4 counter wraps around is used In Delta time mode TSCTR is Reset back to Zero on every valid event Here Capture events are qualified as Rising edge only On an event...

Page 1942: ...ECCTL1 bit CTRRST2 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_DELTA_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECa...

Page 1943: ...and Falling Edge Trigger In Figure 33 12 the eCAP operating mode is almost the same as in previous section except Capture events are qualified as either Rising or Falling edge this now gives both Peri...

Page 1944: ...ODE ECap1Regs ECCTL1 bit CTRRST3 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_DELTA_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECap1Regs ECCTL2 bit CAP_APWM EC_...

Page 1945: ...active low then the compare value represents the off time Note here values are in hexadecimal h notation 33 4 1 Simple PWM Generation Independent Channel s Figure 33 13 PWM Waveform Details of APWM M...

Page 1946: ...FLG Capture Interrupt Flag Register Section 33 5 9 2Eh ECEINT Capture Interrupt Enable Register Section 33 5 10 30h ECFRC Capture Interrupt Forcing Register Section 33 5 11 32h ECCLR Capture Interrupt...

Page 1947: ...egister can be loaded written by Time Stamp counter value during a capture event Software may be useful for test purposes initialization APRD shadow register CAP3 when used in APWM mode 33 5 4 Capture...

Page 1948: ...is is a time stamp capture register In APWM mode this is the period shadow APRD register You update the PWM period value through this register In this mode CAP3 APRD shadows CAP1 33 5 6 Capture 4 Regi...

Page 1949: ...AP module operates in APWM mode This mode forces the following configuration Resets TSCTR on CTR PRD event period boundary Permits shadow loading on CAP1 and 2 registers Disables loading of time stamp...

Page 1950: ...n capture sequence is stopped Wrap value for continuous mode This is the number between 1 4 of the capture register in which the circular buffer wraps around and starts again 0 Stop after Capture Even...

Page 1951: ...Divide by 10 1Eh Divide by 60 1Fh Divide by 62 8 CAPLDEN Enable Loading of CAP1 4 registers on a capture event 0 Disable CAP1 4 register loads at capture event time 1 Enable CAP1 4 register loads at...

Page 1952: ...Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge RE 1 Capture Event 2 triggered on a falling edge FE 1 CTRRST1 Counter Reset on Capture Event 1 0 Do not reset counter on Ca...

Page 1953: ...t occurred 1 Indicates the counter TSCTR reached the period register value APRD and was reset 5 CTROVF Counter Overflow Status Flag This flag is active in CAP and APWM mode 0 Indicates no event occurr...

Page 1954: ...value after reset Table 33 11 ECAP Interrupt Enable Register ECEINT Field Descriptions Bits Field Value Description 15 8 Reserved 0 Reserved 7 CTR_CMP Counter Equal Compare Interrupt Enable 0 Disable...

Page 1955: ...7 CTR_CMP Force Counter Equal Compare Interrupt 0 No effect Always reads back a 0 1 Writing a 1 sets the CTR_CMP flag bit 6 CTR_PRD Force Counter Equal Period Interrupt 0 No effect Always reads back a...

Page 1956: ...eriod Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CTR_PRD flag condition 5 CTROVF Counter Overflow Status Flag 0 Writing a 0 has no effect Always reads back...

Page 1957: ...Module The enhanced quadrature encoder pulse eQEP module is used for direct interface with a linear or rotary incremental encoder to get position direction and speed information from a rotating machi...

Page 1958: ...irection information the lines on the disk are read out by two different photo elements that look at the disk pattern with a mechanical shift of 1 4 the pitch of a line pair between them This shift is...

Page 1959: ...encoders include robotics and even computer input in the form of a mouse Inside your mouse you can see where the mouse ball spins a pair of axles a left right and an up down axle These axles are conne...

Page 1960: ...mer resolution This can introduce considerable error into high speed estimates For systems with a large speed range that is speed estimation is needed at both low and high speeds one approach is to us...

Page 1961: ...ters QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK VCLK3 Data bus To CPU www ti com Basic Operation 1961 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced...

Page 1962: ...x18 2 0 0x00000000 eQEP Position Latch Register QUTMR 0x1C 2 0 0x00000000 eQEP Unit Timer Register QUPRD 0x20 2 0 0x00000000 eQEP Unit Period Register QWDPRD 0x24 1 0 0x0000 eQEP Watchdog Period Regis...

Page 1963: ...EPSTS QDF EQEPA EQEPB www ti com Basic Operation 1963 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module 34 2...

Page 1964: ...ingly updates the direction information in QEPSTS QDF bit Table 34 2 and Figure 34 6 show the direction decoding logic in truth table and state machine form Both edges of the QEPA and QEPB signals are...

Page 1965: ...QEPB as shown in Figure 34 7 Reverse Count In normal quadrature count operation QEPA input is fed to the QA input of the quadrature decoder and the QEPB input is fed to the QB input of the quadrature...

Page 1966: ...ters QEPCTL and QPOSCTL for setting up position counter operational modes position counter initialization latch modes and position compare logic for sync signal generation 34 2 2 3 1 Position Counter...

Page 1967: ...uadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation For example if the first reset operation occurs on the falling edge of QEPB...

Page 1968: ...nter overflow flag is set If the position counter is equal to ZERO then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and position counter underflow flag is set F...

Page 1969: ...3 2 1 Index Event Latch In some applications it may not be desirable to reset the position counter on every index event and instead it may be required to operate the position counter in full 32 bit mo...

Page 1970: ...rature Encoder Pulse eQEP Module Figure 34 10 Software Index Marker for 1000 line Encoder QEPCTL IEL 1 34 2 2 3 2 2 Strobe Event Latch The position counter value is latched to the QPOSSLAT register on...

Page 1971: ...e of strobe input for forward direction and on the falling edge of strobe input for reverse direction Software Initialization SWI The position counter can be initialized in software by writing a 1 to...

Page 1972: ...on 3 to 2 transitions of the eQEP position counter for reverse counting direction see Figure 34 13 Section 34 3 14 shows the layout of the eQEP Position Compare Control Register QPOSCTL and describes...

Page 1973: ...this status flag before reading the period register for low speed measurement and clear the flag by writing 1 Time measurement T between unit position events will be correct if the following conditio...

Page 1974: ...Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module Figure 34 15 eQEP Edge Capture Unit NOTE The QCAPCTL UPPS prescaler should not be mo...

Page 1975: ...on Equations 71 where v k Velocity at time instant k x k Position at time instant k x k 1 Position at time instant k 1 T Fixed unit time or inverse of velocity calculation rate X Incremental position...

Page 1976: ...stem The eQEP watchdog timer is clocked from VCLK3 64 and the quadrate clock event pulse resets the watchdog timer If no quadrature clock event is detected until a period match QWDPRD QWDTMR then the...

Page 1977: ...L and UTO can be generated The interrupt control register QEINT is used to enable disable individual interrupt event sources The interrupt flag register QFLG indicates if any interrupt event has been...

Page 1978: ...EP Position Counter Latch Register Section 34 3 7 1Ch QUTMR eQEP Unit Timer Register Section 34 3 8 20h QUPRD eQEP Unit Period Register Section 34 3 9 24h QWDPRD eQEP Watchdog Period Register Section...

Page 1979: ...34 3 2 eQEP Position Counter Initialization Register QPOSINIT Figure 34 22 eQEP Position Counter Initialization Register QPOSINIT offset 04h 31 0 QPOSINIT R W 0 LEGEND R W Read Write n value after re...

Page 1980: ...h 34 3 5 eQEP Index Position Latch Register QPOSILAT Figure 34 25 eQEP Index Position Latch Register QPOSILAT offset 10h 31 0 QPOSILAT R 0 LEGEND R Read only n value after reset Table 34 8 eQEP Index...

Page 1981: ...28 eQEP Unit Timer Register QUTMR offset 1Ch 31 0 QUTMR R W 0 LEGEND R W Read Write n value after reset Table 34 11 eQEP Unit Timer Register QUTMR Field Descriptions Bits Name Description 31 0 QUTMR T...

Page 1982: ...out count for the eQEP peripheral watchdog timer When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated 34 3 11 eQEP Watchdog Timer Register QWDTMR...

Page 1983: ...naffected by emulation suspend QCTMR behavior 0 Capture timer stops immediately 1h Capture timer counts until next unit period event 2h 3h Capture timer is unaffected by emulation suspend 13 12 PCRM P...

Page 1984: ...edge of the index signal 3h Software index marker Latches the position counter and quadrature direction flag on index event marker The position counter is latched to the QPOSILAT register and the dir...

Page 1985: ...QDIR 1 3h DOWN count mode for frequency measurement QCLK xCLK QDIR 0 13 SOEN Sync output enable 0 Position compare sync output is disabled 1 Position compare sync output is enabled 12 SPSEL Sync outp...

Page 1986: ...ue after reset Table 34 17 eQEP Position Compare Control Register QPOSCTL Field Descriptions Bit Name Value Description 15 PCSHDW Position compare shadow enable 0 Shadow is disabled load Immediate 1 S...

Page 1987: ...APCTL Field Descriptions Bits Name Value Description 15 CEN Enable eQEP capture 0 eQEP capture unit is disabled 1 eQEP capture unit is enabled 14 7 Reserved 0 Always read as 0 6 4 CCPS eQEP capture ti...

Page 1988: ...enerated 1 Set after latching the QPOSCNT to QPOSSLAT 8 PCM Position compare match interrupt flag 0 No interrupt is generated 1 Set on position compare match 7 PCR Position compare ready interrupt fla...

Page 1989: ...tch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 9 SEL Strobe event latch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 8 PCM Position compare match interrupt enab...

Page 1990: ...rupt 0 No effect 1 Force the interrupt 10 IEL Force index event latch interrupt 0 No effect 1 Force the interrupt 9 SEL Force strobe event latch interrupt 0 No effect 1 Force the interrupt 8 PCM Force...

Page 1991: ...terrupt flag 9 SEL Clear strobe event latch interrupt flag 0 No effect 1 Clears the interrupt flag 8 PCM Clear eQEP compare match event interrupt flag 0 No effect 1 Clears the interrupt flag 7 PCR Cle...

Page 1992: ...ture Encoder Pulse eQEP Module 34 3 20 eQEP Capture Timer Register QCTMR Figure 34 40 eQEP Capture Timer Register QCTMR offset 38h 15 0 QCTMR R W 0 LEGEND R W Read Write n value after reset Table 34 2...

Page 1993: ...rotation or reverse movement on the first index event 1 Clockwise rotation or forward movement on the first index event 5 QDF Quadrature direction flag 0 Counter clockwise rotation or reverse movement...

Page 1994: ...counter 34 3 23 eQEP Capture Period Register QCPRD Figure 34 43 eQEP Capture Period Register QCPRD offset 3Eh 15 0 QCPRD R W 0 LEGEND R W Read Write n value after reset Table 34 26 eQEP Capture Period...

Page 1995: ...odulator ePWM Module The enhanced pulse width modulator ePWM peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipments The feat...

Page 1996: ...e first instance and ePWM3 is the third instance in the system and ePWMx indicates any instance The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as...

Page 1997: ...r PLL Slip TZ6n TZ5n TZ4n Debug Mode Entry OSC FAIL or PLL SLip TZ6n TZ5n TZ4n SOCA2 3 4 5 6 SOCB2 3 4 5 6 EPWM2 3 4 5 6INTn EPWM2 3 4 5 6TZINTn EPWM7INTn EPWM7TZINTn VBus32 VBus32 VCLK3 SYS_nRST VBus...

Page 1998: ...unter before connecting to the ePWM modules This selection is done by configuring registers in the IOMM TZ4 is connected to an inverted eQEP1 error signal EQEP1ERR or to an inverted eQEP2 error signal...

Page 1999: ...1 No No Action Qualifier Control Register for Output A EPWMxA AQSFRC 18h 1 No No Action Qualifier Software Force Register AQCTLB 1Ah 1 No No Action Qualifier Control Register for Output B EPWMxB AQCS...

Page 2000: ...hen you should see the counter compare submodule in Section 35 2 3 for relevant details Table 35 2 Submodule Configuration Parameters Submodule Configuration Parameter or Option Time base TB Scale the...

Page 2001: ...none of the trip zone signals or digital compare events Specify the tripping action taken when a fault occurs Force EPWMxA and or EPWMxB high Force EPWMxA and or EPWMxB low Force EPWMxA and or EPWMxB...

Page 2002: ...WM Figure 35 3 Time Base Submodule Block Diagram 35 2 2 1 Purpose of the Time Base Submodule You can configure the time base submodule for the following Specify the ePWM time base counter TBCTR freque...

Page 2003: ...er with the counter of ePWM module earlier in the synchronization chain An ePWM peripheral can be configured to use or ignore this signal For the first ePWM module EPWM1 this signal comes from a devic...

Page 2004: ...The time base counter has three modes of operation selected by the time base control register TBCTL Up Down Count Mode In up down count mode the time base counter starts from zero and increments until...

Page 2005: ...RD shadow register is enabled when TBCTL PRDLD 0 Reads from and writes to the TBPRD memory address go to the shadow register The shadow register contents are transferred to the active register TBPRD A...

Page 2006: ...each ePWM module instance 2 Set TBCLKSYNC 0 This will stop the time base clock within any enabled ePWM module 3 Configure ePWM modules prescaler values and ePWM modes 4 Set TBCLKSYNC 1 35 2 2 3 3 Time...

Page 2007: ...is independent of the direction prior to the synchronization event The PHSDIR bit is ignored in count up or count down modes See Figure 35 7 through Figure 35 10 for examples Clearing the TBCTL PHSEN...

Page 2008: ...R PRD 0xFFFF TBPHS value TBPRD value ePWM Submodules www ti com 2008 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM...

Page 2009: ...lue EPWMxSYNCI CTR_dir CTR zero CNT_max CTR PRD www ti com ePWM Submodules 2009 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Mod...

Page 2010: ...gital Compare Signals Digital Compare Signals VIM 0x0000 0xFFFF TBCTR 15 0 UP DOWN UP DOWN UP DOWN TBPHS value TBPRD value EPWMxSYNCI CTR_dir CTR zero CNT_max CTR PRD ePWM Submodules www ti com 2010 S...

Page 2011: ...e B CMPB registers When the time base counter is equal to one of the compare registers the counter compare unit generates an appropriate event The counter compare Generates events based on programmabl...

Page 2012: ...ow register Shadowing provides a way to keep updates to the registers synchronized with the hardware When shadowing is used updates to the active registers only occur at strategic points This prevents...

Page 2013: ...count mode used to generate a symmetrical PWM waveform To illustrate the operation of the first three modes the timing diagrams in Figure 35 13 through Figure 35 16 show when events are generated and...

Page 2014: ...xSYNCI ePWM Submodules www ti com 2014 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM Module Figure 35 15 Counter C...

Page 2015: ...he EPWMxA and EPWMxB outputs Figure 35 17 Action Qualifier Submodule 35 2 4 1 Purpose of the Action Qualifier Submodule The action qualifier submodule is responsible for the following Qualifying and g...

Page 2016: ...escription Registers Compared CTR PRD Time base counter equal to the period value TBCTR TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 CTR CMPA Time base counter equal to the counter comp...

Page 2017: ...for details Actions are specified independently for either output EPWMxA or EPWMxB Any or all events can be configured to generate actions on a given output For example both CTR CMPA and CTR CMPB can...

Page 2018: ...equals CMPB on up count CBU 6 Lowest Counter equals CMPA on down count CAD Counter equals CMPA on up count CBU Table 35 10 shows the action qualifier priority for up count mode In this case the count...

Page 2019: ...you load CMPA CMPB on period then use CMPA CMPB values less than or equal to TBPRD 1 This means there will always be a pulse of at least one TBCLK cycle in a PWM period which when very short tend to...

Page 2020: ...PWM waveforms in Figure 35 21 through Figure 35 26 show some common action qualifier configurations The C code samples in Example 35 1 through Example 35 6 shows how to configure an ePWM module for ea...

Page 2021: ...m period to 0000 Example 35 1 Code Sample for Figure 35 21 Initialization Time EPwm1Regs TBPRD 600 Period 601 TBCLK counts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 200 Co...

Page 2022: ...WMxB Active Low A PWM period TBPRD 1 TTBCLK B Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA C Duty modulation for EPWMxB is set by CMPB...

Page 2023: ...TBCLK VCLK3 EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EPwm1Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm1Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm1Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs...

Page 2024: ...s TBCTL bit CTRMODE TB_COUNT_UP EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit HSPCLKD...

Page 2025: ...Figure 35 24 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 400 Compare A 400 TBCLK counts EPwm1Regs CMPB 500 Compare B 500 TBCLK counts EPwm1Regs TBPHS 0 S...

Page 2026: ...run time for the waveforms in Figure 35 25 Example 35 5 Code Sample for Figure 35 25 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK...

Page 2027: ...ime for the waveforms in Figure 35 26 Example 35 6 Code Sample for Figure 35 26 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 250 Compare A 250 TBCLK count...

Page 2028: ...to generate the required dead band by having full control over edge placement using both the CMPA and CMPB resources of the ePWM module However if the more classical edge delay based dead band with po...

Page 2029: ...the signal source for each delay falling edge or rising edge can be selected EPWMxA In is the source for both falling edge and rising edge delay This is the default mode EPWMxA In is the source for f...

Page 2030: ...urations that should address all the active high low modes required by available industry power switch gate drivers The waveforms for these typical cases are shown in Figure 35 29 Note that to generat...

Page 2031: ...gh AH Active Low AL RED FED Period www ti com ePWM Submodules 2031 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM M...

Page 2032: ...K Where TTBCLK is the period of TBCLK the prescaled version of VCLK3 For convenience delay values for various TBCLK options are shown in Table 35 15 Table 35 15 Dead Band Delay Values in S as a Functi...

Page 2033: ...to control the power switching elements Figure 35 30 PWM Chopper Submodule 35 2 6 1 Purpose of the PWM Chopper Submodule The key functions of the PWM chopper submodule are Programmable chopping carri...

Page 2034: ...om 2034 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM Module Figure 35 31 PWM Chopper Submodule Operational Detail...

Page 2035: ...d of the first pulse is given by T1stpulse TVCLK3 8 OSHTWTH Where TVCLK3 is the period of the system clock VCLK3 and OSHTWTH is the four control bits value from 1 to 16 Figure 35 33 shows the first an...

Page 2036: ...ircuitry Saturation is one such consideration To assist the gate drive designer the duty cycles of the second and subsequent pulses have been made programmable These sustaining pulses ensure the corre...

Page 2037: ...system oscillator or PLL clock fail logic and TZ6 is sourced from the debug mode halt indication output from the CPU These signals indicate fault or trip conditions and the ePWM outputs can be program...

Page 2038: ...this the trip condition may not be latched The asynchronous trip makes sure that if clocks are missing for any reason the outputs can still be tripped by a valid event present on TZn inputs The GPIOs...

Page 2039: ...e DCTRIPSEL register and can be either trip zone input pins For more information on the digital compare submodule signals see Section 35 2 9 When a digital compare event occurs the action specified in...

Page 2040: ...TZ1 as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5 pulls b...

Page 2041: ...ubmodule DCAEVT1 force DCAEVT2 force DCBEVT1 force DCBEVT2 force TZ1 TZ2 TZ3 DCAEVT2 force DCBEVT2 force TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 Sync DCAEVT1 force DCBEVT1 force www ti com ePWM Submodules 2041 SPNU56...

Page 2042: ...2 TZFLG DCAEVT2 Clear Latch Set TZCLR DCBEVT1 DCBEVT1 inter TZEINT DCBEVT1 TZFLG DCBEVT1 Clear Latch Set TZCLR DCBEVT2 DCBEVT2 inter TZEINT DCBEVT2 TZFLG DCBEVT2 Generate Interrupt Pulse When Input 1...

Page 2043: ...e interrupt requests and ADC start of conversion at Every event Every second event Every third event Provides full visibility of event generation via event counters and flags Allows software forcing o...

Page 2044: ...EPWM6SOCB EPWM7SOCA EPWM7SOCB EPWM7 module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB SOCAEN SOCBEN bits inside ePWMx modules Controlled by PINMMR ePWM Submodules www ti com 2044 SPNU563A March 2018 Submit Docume...

Page 2045: ...d event Figure 35 40 Event Trigger Submodule Showing Event Inputs and Prescaled Outputs The key registers used to configure the event trigger submodule are listed in Table 35 20 Table 35 20 Event Trig...

Page 2046: ...s the ETPS INTCNT bits are incremented until they reach the value specified by ETPS INTPRD When ETPS INTCNT ETPS INTPRD the counter stops counting and its output is set The counter is only cleared whe...

Page 2047: ...n of the event trigger s start of conversion A SOCA pulse generator The ETPS SOCACNT counter and ETPS SOCAPRD period values behave similarly to the interrupt generator except that the pulses are conti...

Page 2048: ...ubmit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM Module Figure 35 43 shows the operation of the event trigger s start of conversion B SOCB...

Page 2049: ...ule The digital compare submodule operation is controlled and monitored through the following registers 1 These registers are writable only in privileged mode 2 The TZDCSEL register is part of the tri...

Page 2050: ...vent signals or the filtered DCEVTFILT event signals can generate a force to the trip zone module a TZ interrupt an ADC SOC or a PWM sync signal force signal DCAEVT1 2 force signals force trip zone co...

Page 2051: ...force 1 0 Sync TBCLK Async 1 0 DCACTL EVT1SRCSEL DCEVTFILT DCAEVT1 DCACTL EVT1FRCSYNCSEL TZFRC DCAEVT1 www ti com ePWM Submodules 2051 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018...

Page 2052: ...VT1 DCBEVT1 inter DCBEVT1 sync DCBCTL EVT1SYNCE async DCEVTFILT DCBCTL EVT1FRCSYNCSEL DCBCTL EVT1SRCSEL ePWM Submodules www ti com 2052 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018...

Page 2053: ...ture the TBCTR value of the trip event Figure 35 49 shows the details of the event filtering logic Figure 35 49 Event Filtering If the blanking logic is enabled one of the digital compare events DCAEV...

Page 2054: ...ng Window Timing Diagram 35 2 10 Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to th...

Page 2055: ...ities The key configuration choices available to each module are as follows Options for SyncIn Load own counter with phase register on an incoming sync strobe enable EN switch closed Do nothing or ign...

Page 2056: ...EN EPWM2B EPWM2A Slave Master SyncIn SyncIn 1 2 0 0 Application Examples www ti com 2056 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse...

Page 2057: ...ntrolling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck A single ePWM module configured as a master can control two buck stages with...

Page 2058: ...iggers an interrupt CB A I P I P I P I Indicates this event triggers an ADC start of conversion Application Examples www ti com 2058 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Te...

Page 2059: ...T_UP Asymmetrical mode EPwm2Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm2Regs CMPCTL bit SHDWAMODE CC_SH...

Page 2060: ...edback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width Modulator ePWM Module 35 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement eP...

Page 2061: ...A P CA CA CB CB CB CB CA CA CA CA CB CB CB CB www ti com Application Examples 2061 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse Width...

Page 2062: ...m1Regs AQCTLB bit CBU AQ_SET set actions for EPWM1B EPwm1Regs AQCTLB bit CBD AQ_CLEAR EPWM Module 2 config EPwm2Regs TBPRD 600 Period 1200 TBCLK counts EPwm2Regs TBPHS half TBPHS 0 Set Phase register...

Page 2063: ...ing elements can also be addressed with these same ePWM modules It is possible to control a Half H bridge stage with a single ePWM module This control can be extended to multiple stages Figure 35 57 s...

Page 2064: ...CA Pulse Center Z A CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA Application Examples www ti com 2064 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated...

Page 2065: ...DWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit...

Page 2066: ...reg 3 Slave SyncOut X En EPWM3B EPWM3A Phase reg CTR CMPB CTR zero 4 Slave SyncOut X EPWM4A EPWM4B En SyncOut CTR zero CTR CMPB Phase reg Phase reg CTR CMPB CTR zero Slave 6 5 Slave X En SyncIn EPWM6...

Page 2067: ...Z I A P CA CA Z I A P CA CA CA CA CA CA CA CA CA CA www ti com Application Examples 2067 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Enhanced Pulse...

Page 2068: ...ve made use of the phase register TBPHS It has either been set to zero or its value has been a don t care However by programming appropriate values into TBPHS multiple PWM modules can address another...

Page 2069: ...Incorporated Enhanced Pulse Width Modulator ePWM Module Figure 35 62 shows the associated timing waveforms for this configuration Here TBPRD 600 for both master and slave For the slave TBPHS 200 200...

Page 2070: ...35 4 3 3 1Eh AQCSFRC Action Qualifier Continuous S W Force Register Set Section 35 4 3 4 Dead Band Generator Submodule Registers 1Ch DBCTL Dead Band Generator Control Register Section 35 4 4 1 20h DBF...

Page 2071: ...0 R W1C 0 R W1C 0 R 1 LEGEND R W Read Write R Read only W1C Write 1 to clear n value after reset Table 35 23 Time Base Status Register TBSTS Field Descriptions Bit Field Value Description 15 3 Reserv...

Page 2072: ...wn count mode stop when the time base counter 0x0000 TBCTR 0x0000 Up down count mode stop when the time base counter 0x0000 TBCTR 0x0000 2h 3h Free run 13 PHSDIR Phase Direction Bit This bit is only u...

Page 2073: ...ister TBPRD is loaded from its shadow register when the time base counter TBCTR is equal to zero A write or read to the TBPRD register accesses the shadow register 1 Load the TBPRD register immediatel...

Page 2074: ...ter reset Table 35 26 Time Base Period Register TBPRD Field Descriptions Bits Name Description 15 0 TBPRD These bits determine the period of the time base counter This sets the PWM frequency Shadowing...

Page 2075: ...not full yet 1 Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value 7 Reserved 0 Reserved 6 SHDWBMODE Counter compare B CMPB Register Operating Mode 0 Shadow mode...

Page 2076: ...ng on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include Do nothing the event is ignored Clear Pull the EPWMxA and or EPWMx...

Page 2077: ...ding on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include Do nothing event is ignored Clear Pull the EPWMxA and or EPWMxB...

Page 2078: ...utput signal will be forced high and a high signal will be forced low 7 6 CAD Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action is disabled 1h...

Page 2079: ...CPU and is not loaded from the shadow register 5 OTSFB One Time Software Forced Event on Output B 0 Writing a 0 has no effect Always reads back a 0 This bit is auto cleared once a write to this regist...

Page 2080: ...high and a high signal will be forced low 7 6 CAD Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action is disabled 1h Clear force EPWMxB output...

Page 2081: ...Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To...

Page 2082: ...oth falling and rising edge delays 0 EPWMxA In from the action qualifier is the source for both falling edge and rising edge delay 1h EPWMxB In from the action qualifier is the source for rising edge...

Page 2083: ...om the action qualifier are passed directly to the PWM chopper submodule In this mode the POLSEL and IN_MODE bits have no effect 1h Disable rising edge delay The EPWMxA signal from the action qualifie...

Page 2084: ...r reset Table 35 36 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions Bits Name Description 15 10 Reserved Reserved 9 0 DEL Falling Edge Delay Count 10 bit counter 35 4 4 3 Dead...

Page 2085: ...ut B Event 2 Selection 0 Event is disabled 1h DCBH low DCBL don t care 2h DCBH high DCBL don t care 3h DCBL low DCBH don t care 4h DCBL high DCBH don t care 5h DCBL high DCBH low 6h 7h Reserved 8 6 DC...

Page 2086: ...t 0 Disable TZ6 as a one shot trip source for this ePWM module 1 Enable TZ6 as a one shot trip source for this ePWM module 12 OSHT5 Trip zone 5 TZ5 Select 0 Disable TZ5 as a one shot trip source for t...

Page 2087: ...Z5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module 3 CBC4 Trip zone 4 TZ4 Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 a...

Page 2088: ...alue Description 15 3 Reserved 0 Reserved 6 DCBEVT2 Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled 5 DCBEVT1 Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled...

Page 2089: ...gh state 2h Force EPWMxB to a low state 3h Do Nothing trip action is disabled 7 6 DCAEVT2 Digital Compare Output A Event 2 Action On EPWMxA 0 High impedance EPWMxA High impedance state 1h Force EPWMxA...

Page 2090: ...This bit always reads back 0 1 Writing 1 clears the DCBEVT1 event trip condition 4 DCAEVT2 Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect This bit always reads back 0 1 Writ...

Page 2091: ...Status Flag for A One Shot Trip Event 0 No one shot trip event has occurred 1 A trip event has occurred on a pin selected as a one shot trip source This bit is cleared by writing the appropriate value...

Page 2092: ...TZFLG DCBEVT2 bit 5 DCBEVT1 Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect This bit always reads back 0 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZF...

Page 2093: ...n count mode 4h Enable event time base counter equal to CMPA when the timer is incrementing 5h Enable event time base counter equal to CMPA when the timer is decrementing 6h Enable event time base cou...

Page 2094: ...offset 34h 15 8 Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 35 46 Event Trigger Flag Register ETFLG Field Descriptions Bit...

Page 2095: ...B 1 Once the SOCB pulse is generated the ETPS SOCBCNT bits will automatically be cleared 0 Disable the SOCB event counter No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the fi...

Page 2096: ...nts need to occur before an interrupt is generated To be generated the interrupt must be enabled ETSEL INT 1 If the interrupt status flag is set from a previous interrupt ETFLG INT 1 then no interrupt...

Page 2097: ...ETSEL register The ETFLG SOCB flag bit will be set regardless 0 Has no effect Always reads back a 0 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit This bit is used for test purposes 2 SOCA...

Page 2098: ...Table 35 49 Event Trigger Clear Register ETCLR Field Descriptions Bits Name Value Description 15 4 Reserved 0 Reserved 3 SOCB ePWM ADC Start of Conversion B EPWMxSOCB Flag Clear Bit 0 Writing a 0 has...

Page 2099: ...35 50 PWM Chopper Control Register PCCTL Bit Descriptions Bits Name Value Description 15 11 Reserved 0 Reserved 10 8 CHPDUTY Chopping Clock Duty Cycle 0 Duty 1 8 12 5 1h Duty 2 8 25 0 2h Duty 3 8 37...

Page 2100: ...20 nS at 100 MHz VCLK3 4h 5 x VCLK3 8 wide 400 nS at 100 MHz VCLK3 5h 6 x VCLK3 8 wide 480 nS at 100 MHz VCLK3 6h 7 x VCLK3 8 wide 560 nS at 100 MHz VCLK3 7h 8 x VCLK3 8 wide 640 nS at 100 MHz VCLK3 8...

Page 2101: ...al Compare A Control Register DCACTL Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reserved 9 EVT2FRC SYNCSEL DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Sign...

Page 2102: ...Digital Compare B High Input Select Defines the source for the DCBH input The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low 0 TZ1 in...

Page 2103: ...set Table 35 53 Digital Compare Filter Control Register DCFCTL Field Descriptions Bit Field Value Description 15 6 Reserved 0 Reserved 5 4 PULSESEL Pulse Select For Blanking Capture Alignment 0 Time b...

Page 2104: ...Register DCBCTL Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reserved 9 EVT2FRC SYNCSEL DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynch...

Page 2105: ...n when the active register is loaded When the counter expires the blanking window is applied If the blanking window is currently active then the blanking window counter is restarted 35 4 8 6 Digital C...

Page 2106: ...ter is loaded and begins to count down If the blanking window is currently active and the offset counter expires the blanking window counter is restarted The blanking window can cross a PWM period bou...

Page 2107: ...adowed If DCCAPCTL SHDWMODE 0 then the shadow is enabled In this mode the active register is copied to the shadow register on the TBCTR TBPRD or TBCTR zero as defined by the DCFCTL PULSESEL bit CPU re...

Page 2108: ...18 Data Modification Module DMM This chapter describes the functionality of the Data Modification Module DMM which provides the capability to modify data in the entire 4 GB address space of the device...

Page 2109: ...g features Acts as a bus master thus enabling direct writes to the 4GB address space without CPU intervention Writes to memory locations specified in the received packet leverages packets defined by t...

Page 2110: ...er is completely full the data will be moved to the output buffer register A two level buffer is implemented to avoid overflow conditions if the internal bus is occupied by other transactions In addit...

Page 2111: ...tting hardware module has occurred If this is the case the SRC_OVF flag Section 36 3 5 will be set and the received data will be written to the address specified in the packet The size information of...

Page 2112: ...ceived before the expected number of bits 36 2 2 Data Port The packet will be received in several subpackets depending on the width of the external data bus DMMDATA y 0 and the amount of data to be tr...

Page 2113: ...the start of a packet and will flag a PACKET_ERR_INT Section 36 3 5 DMMCLK The clock is externally generated and can be suspended between two packets For this feature CONTCLK must be set to 0 Section...

Page 2114: ...e detection of the first DMMSYNC signal after the DMM is turned on or comes out of suspend mode with COS 0 Section 36 3 1 that is before the reception of first DMMSYNC the toggling of DMMCLK would be...

Page 2115: ...on 36 3 6 18h DMMOFF2 DMM Interrupt Offset 2 Register Section 36 3 7 1Ch DMMDDMDEST DMM Direct Data Mode Destination Register Section 36 3 8 20h DMMDDMBL DMM Direct Data Mode Blocksize Register Sectio...

Page 2116: ...ts internal buffers 23 19 Reserved 0 Reads returns 0 Writes have no effect 18 CONTCLK Continuous DMMCLK input User and privilege mode read privilege mode write 0 DMMCLK is expected to be suspended bet...

Page 2117: ...other The DMM module does not receive data Ah The DMM module receives data and writes it to the buffer Privilege mode write All other Disable receive write operations Packets in reception will still b...

Page 2118: ...le Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register Section 36 3 11 This bit is only relevant in Direct Data M...

Page 2119: ...e mode read 0 No interrupt will be generated 1 An interrupt will be generated on a write to the start address of this region Privilege mode write 0 No influence on bit 1 Enable interrupt sets correspo...

Page 2120: ...erflow This enables the interrupt generation in case new data is received while the previous data still has not been transmitted User and privilege mode read 0 No interrupt will be generated 1 An inte...

Page 2121: ...0 or a reserved value the interrupt will still be generated the write to the internal RAM however will not take place User and privilege mode read 0 No interrupt will be generated 1 An interrupt will...

Page 2122: ...n value after reset Table 36 9 DMM Interrupt Clear Register DMMINTCLR Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads returns 0 Writes have no effect 17 PROG_BUFF Programmable B...

Page 2123: ...EG2 Destination 2 Region 2 Interrupt Set This disables the interrupt generation in case data was accessed at the start address of Destination 2 Region 2 This bit is only relevant in Trace Mode User an...

Page 2124: ...te 0 No influence on bit 1 Disable interrupt clears corresponding bit in DMMINTCLR DMM Interrupt Level Register DMMINTLVL 8 DEST0REG1 Destination 0 Region 1 Interrupt Set This disables the interrupt g...

Page 2125: ...e 0 No influence on bit 1 Disable interrupt clears corresponding bit in DMMINTCLR DMM Interrupt Level Register DMMINTLVL 3 DEST2_ERR Destination 2 Error Interrupt Set This disables the interrupt gener...

Page 2126: ...rupt will still be generated the write to the internal RAM however will not take place User and privilege mode read 0 No interrupt will be generated 1 An interrupt will be generated Privilege mode wri...

Page 2127: ...returns 0 Writes have no effect 17 PROG_BUFF Programmable Buffer Interrupt Level User and privilege mode read privilege mode write 0 Interrupt mapped to level 0 1 Interrupt mapped to level 1 16 EO_BU...

Page 2128: ...BUFF_OVF Write Buffer Overflow Interrupt Level User and privilege mode read privilege mode write 0 Interrupt mapped to level 0 1 Interrupt mapped to level 1 5 SRC_OVF Source Overflow Interrupt Level U...

Page 2129: ...d Write R Read only WP Write in privilege mode only C Clear n value after reset Table 36 11 DMM Interrupt Flag Register DMMINTFLG Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads...

Page 2130: ...0 No influence on bit 1 Bit will be cleared 11 DEST1REG2 Destination 1 Region 2 Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influ...

Page 2131: ...0 No influence on bit 1 Bit will be cleared 5 SRC_OVF Source Overflow Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influence on bi...

Page 2132: ...criptions continued Bit Field Value Description 1 DEST0_ERR Destination 0 Error Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influ...

Page 2133: ...DMMOFF1 Field Descriptions Bit Field Value Description 31 5 Reserved 0 Read returns 0 Writes have no effect 4 0 OFFSET User and privilege mode read Bit Encoding Interrupt 0 Phantom All interrupt flag...

Page 2134: ...DMMOFF1 Field Descriptions Bit Field Value Description 31 5 Reserved 0 Read returns 0 Writes have no effect 4 0 OFFSET User and privilege mode read Bit Encoding Interrupt 0 Phantom All interrupt flag...

Page 2135: ...f the blocksize chosen in DMMDDMBL Section 36 3 9 User and privilege mode read current start address Privilege mode write sets start address to value written 36 3 9 DMM Direct Data Mode Blocksize Regi...

Page 2136: ...in 32 bit DDM mode bit 0 and 1 will be 0 User and privilege mode read next data entry Privilege mode write writes have no effect 36 3 11 DMM Direct Data Mode Interrupt Pointer Register DMMINTPT This r...

Page 2137: ...ion x Region 1 DMMDESTxREG1 offset 2Ch 3Ch 4Ch 5Ch 31 18 17 16 BASEADDR BLOCKADDR R WP 0 R WP 0 15 0 BLOCKADDR R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 36...

Page 2138: ...L1 DMMDEST3BL1 Figure 36 19 DMM Destination x Blocksize 1 DMMDESTxBL1 offset 30h 40h 50h 60h 31 16 Reserved R 0 15 4 3 0 Reserved BLOCKSIZE R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in pri...

Page 2139: ...ion x Region 2 DMMDESTxREG2 offset 34h 44h 54h 64h 31 18 17 16 BASEADDR BLOCKADDR R WP 0 R WP 0 15 0 BLOCKADDR R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 36...

Page 2140: ...L2 DMMDEST3BL2 Figure 36 21 DMM Destination x Blocksize 2 DMMDESTxBL2 offset 38h 48h 58h 68h 31 16 Reserved R 0 15 4 3 0 Reserved BLOCKSIZE R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in pri...

Page 2141: ...ND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 36 22 DMM Pin Control 0 DMMPC0 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0...

Page 2142: ...DIR R 0 R WP 0 R WP 0 R WP 0 15 14 13 12 11 10 9 8 DATA13DIR DATA12DIR DATA11DIR DATA10DIR DATA9DIR DATA8DIR DATA7DIR DATA6DIR R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 D...

Page 2143: ...DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode read 0 Pin is used as input 1 Pin is used as output Privilege mode write 0 Pin is set to inp...

Page 2144: ...n Control 2 DMMPC2 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAIN DMMENA input This bit reflects the state of the pin in all modes User...

Page 2145: ...tions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAOUT Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode r...

Page 2146: ...SET DATA8SET DATA7SET DATA6SET R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 DATA5SET DATA4SET DATA3SET DATA2SET DATA1SET DATA0SET CLKSET SYNCSET R WP 0 R WP 0 R WP 0 R WP 0...

Page 2147: ...User and privilege mode read 0 Logic low output voltage is V OL or lower 1 Logic high output voltage is V OH or higher Privilege mode write 0 State of the pin is unchanged 1 Logic high output voltage...

Page 2148: ...ads returns 0 Writes have no effect 18 ENACLR Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in t...

Page 2149: ...pin to pull it high when the pin is in high impedance mode Figure 36 28 DMM Pin Control 6 DMMPC6 offset 84h 31 24 Reserved R 0 23 19 18 17 16 Reserved ENAPDR DATA15PDR DATA14PDR R 0 R WP 0 R WP 0 R WP...

Page 2150: ...the pin as open drain 1 CLKPDR Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output DMMPC0 1 0 DMMPC1 1 1 If the pin is configured as a functional pin DMMPC0 1...

Page 2151: ...nly n value after reset Table 36 29 DMM Pin Control 7 DMMPC7 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAPDIS Pull disable Removes inter...

Page 2152: ...12 11 10 9 8 DATA13PSEL DATA12PSEL DATA11PSEL DATA10PSEL DATA9PSEL DATA8PSEL DATA7PSEL DATA6PSEL R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 7 6 5 4 3 2 1 0 DATA5PSEL DATA4PSEL DATA3PSEL...

Page 2153: ...p or pulldown functionality if DMMPC7 1 0 User and privilege mode read 0 Pulldown functionality is enabled 1 Pullup functionality is enabled Privilege mode write 0 Enables pulldown functionality 1 Ena...

Page 2154: ...er 37 SPNU563A March 2018 RAM Trace Port RTP This chapter describes the functionality of the RAM trace port RTP module It allows the capability to perform data trace of a CPU or other master accesses...

Page 2155: ...de Trace Mode Section 37 2 1 Non intrusive data trace on write or read operation Visibility of RAM content at any time on external capture hardware Trace of peripheral accesses 2 configurable trace re...

Page 2156: ...FIFO1 FIFO2 FIFO3 FIFO4 RAM Trace Port SERIALIZER RTPENA RTPSYNC RTPCLK RTPDATA x RTPDATA 0 Overview www ti com 2156 SPNU563A March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments...

Page 2157: ...If a FIFO does not hold new data it will be skipped This scheme ensures that the FIFOs are drained uniformly NOTE This device implements Level 1 cache memory Reading and writing from to Level 2 RAMs w...

Page 2158: ...entry in the FIFO will not be overwritten by the new data Table 37 3 Encoding of SIZE bits in Trace Mode Packet Format SIZE 1 0 Write Read Size 0 8 bit 1h 16 bit 2h 32 bit 3h 64 bit Table 37 4 Encodi...

Page 2159: ...amming of the trace regions for all FIFOs will be ignored and data tracing when accessing the addresses defined by the regions will not occur If the module is configured in read mode DDM_RW 0 and if t...

Page 2160: ...ed If only one address range should be excluded from the trace either the address range has to be covered by both regions e g excluding 1kB range with two 512B regions or both regions have to be progr...

Page 2161: ...n the RTP global status register RTPGSR will be set Figure 37 6 FIFO Overflow Handling 37 2 5 Signal Description Table 37 6 lists the signals of the RTP Table 37 6 RTP Signals Signal Description RTPCL...

Page 2162: ...ket transmissions in Trace Mode with an interruption between packets because of RTPENA pulled high Figure 37 7 RTP Packet Transfer with Sync Signal Figure 37 8 shows an example of a 4 bit data port wi...

Page 2163: ...the pin to a low output voltage VOL or lower whereas writing a 1 to the data output register RTPPC3 forces the pin to a high impedance state The open drain functionality is disabled when the pin is c...

Page 2164: ...ry Each FIFO entry is aligned to a 128 bit boundary See Table 37 9 for a listing of the FIFOs and their corresponding addresses Read 0 FIFO RAM is not accessible in the memory map 1 FIFO RAM is mapped...

Page 2165: ...e state machine and the registers to their reset value This reset ensures that no data left in the FIFOs is shifted out after switching on the module with the ON OFF bit Read 0 RTP module is out of re...

Page 2166: ...Ah Tracing of data is enabled All other values Tracing of data is disabled Write in Privilege Ah Enable Tracing of data If there is any previous captured data remaining it will be shifted out All oth...

Page 2167: ...O4 is disabled Read 0 Tracing is disabled 1 Tracing is enabled Write in Privilege 0 Disable tracing If RTPGLBCTRL ON OFF Ah data already captured in FIFO4 is still transmitted RTPGLBCTRL 1 Enable trac...

Page 2168: ...t Field Value Description 0 ENA1 Enable tracing for RAM block 1 This bit enables tracing into FIFO1 in Trace Mode read write or Direct Data Mode read operations In Direct Data Mode write operations th...

Page 2169: ...PER2 Peripheral FIFO empty This bit determines if there are entries left in the FIFO FIFO4 is used for tracing peripherals under PCR3 0 FIFO4 contains entries 1 FIFO4 is empty 10 EMPTYPER1 Peripheral...

Page 2170: ...it occurred The bit will not be cleared automatically if the FIFO is emptied again The bit will stay set until the CPU clears it Read 0 No overflow occurred 1 An overflow occurred Write in Privilege 0...

Page 2171: ...from the other non CPU master 3h Reserved 28 RW Read Write This bit indicates if read or write operations are traced in Trace Mode or Direct Data Mode read operation If configured for write in Direct...

Page 2172: ...ming from the other master 3h Reserved 28 RW Read Write This bit indicates if read or write operations are traced in Trace Mode or Direct Data Mode read operation If configured for write in Direct Dat...

Page 2173: ...trace protocol with 18 bits of address trace out Figure 37 14 and Table 37 15 illustrate these registers Figure 37 14 RTP RAM 3 Trace Region Registers RTPRAM3REGn offset 1Ch and 20h 31 29 28 27 24 23...

Page 2174: ...outside the region defined by the start address and blocksize will be traced If all bits of BLOCKSIZE are 0 the region is disabled and no data will be captured Region size in bytes 0 0 1h 256 2h 512 3...

Page 2175: ...lege mode write 0 Read or write operations are traced when coming from the CPU and the other master 1h Read or write operations are traced only when coming from the CPU 2h Read or write operations are...

Page 2176: ...te Register RTPDDMW offset 2Ch 31 0 DATA R W 0 LEGEND R W Read Write n value after reset Table 37 17 RTP Direct Data Mode Write Register RTPDDMW Field Descriptions Bit Field Description 31 0 DATA This...

Page 2177: ...rol 0 Register RTPPC0 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads return 0 Writes have no effect 18 ENAFUNC Functional mode of RTPENA pin Read 0 Pin is used in GIO mode 1 Pin...

Page 2178: ...is configured in functional mode Read 0 Pin is used as input 1 Pin is used as output Write 0 Configure pin to input mode 1 Configure pin to output mode 17 CLKDIR Direction of RTPCLK pin This bit defi...

Page 2179: ...he state of the pin in all modes Writes to this bit have no effect 0 The pin is at logic low 0 input voltage is V IL or lower 1 The pin is at logic high 1 input voltage is V IH or higher 17 CLKIN RTPC...

Page 2180: ...or higher Write 0 Set pin to logic low 0 output voltage is V OL or lower 1 Set pin to logic high 1 output voltage is V OH or higher 17 CLKOUT RTPCLK output This pin sets the output state of the RTPCLK...

Page 2181: ...ogic high 1 output voltage is V OH or higher Write 0 No effect 1 Set pin to logic high 1 output voltage is V OH or higher 17 CLKSET Sets the output state of RTPCLK pin to logic high Value in the CLKSE...

Page 2182: ...ut logic high 1 output voltage is V OH or higher Write 0 No effect 1 Set pin to logic low 0 output voltage is V OL or lower 17 CLKCLR Sets output state of RTPCLK pin to logic low Value in the CLKCLR b...

Page 2183: ...drain functionality on the pin if it is configured as a GIO output RTPPC0 18 0 RTPPC1 18 1 If the pin is configured as a functional pin RTPPC0 18 1 the open drain functionality is disabled Read 0 Pin...

Page 2184: ...5 0 DATAPDR n RTPDATA 15 0 Open drain enable These bits enable open drain functionality on the pins if they are configured as a GIO output RTPPC0 15 0 0 RTPPC1 15 0 1 If the pins are configured as a f...

Page 2185: ...RTPPC1 18 0 Read 0 Pullup pulldown functionality is enabled 1 Pullup pulldown functionality is disabled Write 0 Enables pullup pulldown functionality 1 Disables pullup pulldown functionality 17 CLKDI...

Page 2186: ...on 31 19 Reserved 0 Reads return 0 Writes have no effect 18 ENAPSEL RTPENA Pull select This bit configures pullup or pulldown functionality if RTPPC7 18 0 Read 0 Pulldown functionality is enabled 1 Pu...

Page 2187: ...18 Texas Instruments Incorporated eFuse Controller Chapter 38 SPNU563A March 2018 eFuse Controller This chapter describes the eFuse controller Topic Page 38 1 Overview 2188 38 2 Introduction 2188 38 3...

Page 2188: ...roup one channel 40 error is sent to the ESM If an error occurs during the eFuse controller self test then a group one channel 41 error and a group one channel 40 error are sent to the ESM After reset...

Page 2189: ...01C with 0x003C0000 to clear the error signals Verify that ESM group 1 channel 41 and group 3 channel 1 are set then clear them If the system cannot support a test which causes the ERROR pin to go low...

Page 2190: ...self test Class 2 error routine Y N Test bits 4 0 of eFuse Error status register Are all 5 bits zero Are the 5 bits 0x15 Class 3 error routine Run eFuse self test Did self test pass eFuse Controller T...

Page 2191: ...egister is also used to initiate an eFuse controller ECC self test Figure 38 2 EFC Boundary Control Register EFCBOUND offset 1Ch 31 24 Reserved R 0 23 22 21 20 19 18 17 16 Reserved EFC Self Test Error...

Page 2192: ...Single Bit Error OE The single bit error output enable signal determines if the EFC Single Bit Error signal comes from the eFuse controller or from bit 20 of the boundary register 0 EFC Single Bit Err...

Page 2193: ...ete 14 EFC Selftest Error This bit indicates the pass fail status of the EFC ECC Selftest once the EFC Selftest Done bit bit 15 is set 0 EFC ECC Selftest passed 1 EFC ECC Selftest failed 13 Reserved 0...

Page 2194: ...instruction executed by the eFuse Controller 0 No error 5h An uncorrectable multibit error was detected during the power on autoload sequence 15h At least one single bit error was detected and correc...

Page 2195: ...0 LEGEND R W Read Write n value after power on reset nPORRST Table 38 7 EFC Self Test Cycles Register EFCSTSIG Field Descriptions Bit Name Description 31 0 Signature This register is used to hold the...

Page 2196: ...table to reflect updated register bit fields 179 Table 2 49 Changed Description of OSCFRQCONFIGCNT bit Writes have no effect 180 Figure 2 38 Changed Reserved bits to 7 5 and SEL_ECP_PIN bits to 4 0 18...

Page 2197: ...r bit name to PS 23 16 QUAD 3 0 PROTCLR 228 Table 2 96 Changed register bit name to PS 23 16 QUAD 3 0 PROTCLR 228 Table 2 96 Corrected register names in Description of PROTCLR bit for Value 1 Write 22...

Page 2198: ...es renumbered 357 Figure 7 26 Changed default value of PSLEEP bit to C8h 368 Table 7 45 Updated Description of SECT_ERASED bit 381 Table 7 46 Updated Description of SECT_ERASED bit 381 Chapter 8 Level...

Page 2199: ...e formula to 512 TOSCIN 530 Section 14 5 4 Added last sentence to step 3 in both paragraphs 532 Figure 14 11 Corrected symbols in figure 539 Figure 14 11 Changed PF block to CP 539 Section 14 8 Change...

Page 2200: ...ure 20 23 Updated Read Write value of HWCHENA bit to R WP 0 727 Figure 20 24 Updated Read Write value of HWCHDIS bit to R WP 0 727 Figure 20 25 Updated Read Write value of SWCHENA bit to R WP 0 728 Fi...

Page 2201: ...served 759 Figure 20 70 Updated Read Write value of DMADBGS bit to R W1C 0 762 Figure 20 80 Updated Read Write value of EDFLAG bit to R W1C 0 767 Figure 20 82 Updated Read Write value of bits to R W1C...

Page 2202: ..._G2 bit The Group2 conversion is kept frozen while the Event Group or Group1 conversion is active 894 Table 22 28 Changed Description for DMA_G2_END bit Corrected group number to 2 911 Figure 22 53 De...

Page 2203: ...es renumbered 1187 Section 25 3 1 Changed description of Data direction in first bullet 1187 Section 25 3 1 Changed description of Open drain in sixth bullet 1187 Section 25 3 1 Changed description of...

Page 2204: ...h FFh 1468 Table 27 18 Updated Description of Message Number bit Only values 1h 40h are valid Values 41h FFh are invalid 1468 Figure 27 32 Corrected register bit name to ABO_TIME 1469 Table 27 19 Corr...

Page 2205: ...7 to PCURRENT 1583 Table 28 43 Changed PSTART bits to 15 8 and PCURRENT bits to 7 0 1583 Table 28 43 Changed Value column of PSTART bits and PCURRENT bits to 0 FFh 1583 Table 28 43 Updated Description...

Page 2206: ...le 1803 Figure 32 7 Added figure Subsequent figures renumbered 1815 Figure 32 8 Added figure Subsequent figures renumbered 1816 Figure 32 9 Added figure Subsequent figures renumbered 1817 Figure 32 28...

Page 2207: ...ption of all bits to Privilege mode write 2149 Figure 36 29 Updated Read Write value of all bits to R WP x 2151 Figure 36 29 Updated LEGEND to include WP 2151 Table 36 29 Changed Description of all bi...

Page 2208: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

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