2+2+2+1+17+2 x8 bit
SIZE
RAM[1:0]
STAT[1:0]
SIZE[1:0]
WR_DATA[xx:0]
ADDR[16:0]
REG
2+2+2+18+2 x8 bit
SIZE
RAM[1:0]
STAT[1:0]
SIZE[1:0]
ADDR[17:0]
WR_DATA[xx:0]
Module Operation
2157
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
37.2 Module Operation
The RTP module has two modes of operation: Trace Mode and Direct Data Mode.
37.2.1 Trace Mode
This mode traces all write or read accesses of CPU and/or a different master to the internal RAMs and the
peripheral bus, if the access falls into one of the programmed trace regions. The trace regions allow to
restrict the amount of data which is traced. This is done by specifying the start address and the size of the
region to be traced. It is not possible to trace write and read operations in the same region at the same
time.
Whenever a write or read access occurs, the address, data, size of the access (8, 16, 32, 64 bit), and
which module initiated the write or read operation is captured into the FIFO of the corresponding RAM
frame. Once new data is in the FIFO and the serializer is empty, the RTP transmits the data into the
serializer and starts transmitting it.
The FIFOs are shifting data into the serializer in a round-robin scheme. This means if data is available in
multiple FIFOs, the sequence for shifting data into the serializer is FIFO1, FIFO2, FIFO3 and then FIFO4.
Only one entry in the respective FIFO is provided to the serializer before switching to the next FIFO. If a
FIFO does not hold new data, it will be skipped. This scheme ensures that the FIFOs are drained
uniformly.
NOTE:
This device implements Level 1 cache memory. Reading and writing from/to Level 2 RAMs
which is declared Cacheable can result in RAM traces that do not correspond to the
software's original intent. Reading from Level 2 RAMs which is declared Cacheable will not
result in any load transaction if the address is a hit in the level 1 cache memory. If a write-
through with allocate on reads policy is selected and a cache miss happens, the cache
controller will also allocate (load) the matching cache line from level 2 RAM after the data is
written to the Level 2 RAM. This load due to the allocate on reads policy will result in the
read data being traced.
37.2.1.1 Packet Format in Trace Mode
and
illustrate this format.
Figure 37-2. Packet Format Trace Mode for RAM Locations
Figure 37-3. Packet Format Trace Mode for Peripheral Locations
When RAM locations are traced, one packet consists of two bits denoting the RAM block in which the data
is stored or if the access has been to a peripheral location (
), two status bits showing the
access initiator or if there was a FIFO overflow (
), two bit size (8, 16, 32, or 64 bit) information
of the data (
), the 18-bit address for RAM accesses and 2
SIZE
× 8 bits of data. If a peripheral
location is traced, then the effective address reduces to 17 bits(ADDR[16:0]) and a separate bit (REG)
between the SIZE information and the address denotes which programmable region has traced this
peripheral access (
). With the region identifier, the external hardware can determine which
peripheral was traced.
