Basic Operation
1503
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.2.2.1 Data Handling for TX and RX Transfer Groups
28.2.2.1.1 Data Sequencing of a Transmit Data
In multi-buffer mode, any buffer that needs to be transmitted over by the SPI, should be associated with a
Transfer Group. Each TG (Transfer Group) will have a Trigger Source based on which it’ll be triggered.
Once a TG is triggered, the buffers belonging to it will be transmitted.
Sequencer (FSM) controls the data flow from the multi-buffer RAM to the Shift Register. The Multi-buffer
Control Logic has arbitration logic between VBUS and the Sequencer accessing the multi-buffer RAM.
Sequencer picks up a highest priority Transfer Group from among the active TGs to be serviced. For the
selected TG the starting buffer to be transferred is obtained from the PSTART of the respective TGxCTRL
register.
Sequencer requests for the selected buffer through the Multi-buffer Control Logic, and once it receives the
data, it reads the control fields to determine the subsequent action. Once the buffer is determined to be
ready for transfer, the data is written to the TX SHIFT REGISTER by the Sequencer. This triggers the
Kernel FSM to initiate the SPI transfer.
Once the Sequencer is finished writing to the TX SHIFT REGISTER, it prefetches the next buffer to be
transferred from the multi-buffer RAM and stores the Data.
Once the Sequencer is finished writing to the TX SHIFT REGISTER, it prefetches the next buffer to be
transferred from the multi-buffer RAM and stores the Data.
Sequencer writes the prefetched Transmit Data to the Shift Register immediately upon request by the
Kernel. This way, the throughput of the SPI transfer is increased in Master mode of operation. In case of
Slave mode, after the Receive data is copied to the RX RAM, Sequencer waits for the next active Chip
Select trigger to fetch the next data.
28.2.2.1.2 Data Sequencing of the Received Data
At the end of a SPI transfer, the received Data is copied to SPIBUF register and then forwarded to the
Sequencer. The Sequencer then, requests the Multi-buffer Control Logic to write the received data to the
respective RXRAM location. Along with Received Data, the Status fields like Transmission Error Flags and
the Last Chip Select Number (LCSNR) are forwarded to be updated in the Status Field of the RXRAM.
Sequencer clears the RXEMPTY bit while writing a new Received Data in the RXRAM. If the RXEMPTY
bit is already 0, then the Sequencer sets the RCVR_OVRN bit to 1 to indicate that this particular location
has been overwritten in the RXRAM.
28.2.3 DMA Requests
In order to reduce CPU overhead in handling SPI message traffic on a character-by-character basis, SPI
can use the DMA controller to transfer the data
28.2.3.1 SPI/MibSPI Compatibility Mode DMA Requests
. The DMA request enable bit (DMA REQ EN) controls the assertion of requests to the DMA controller
module. When a character is being transmitted or received, the SPI will signal the DMA via the DMA
request signals, TX_DMA_REQ and RX_DMA_REQ. The DMA controller will then perform the required
data transfer.
For efficient behavior during DMA operations, the transmitter empty and receive-buffer full interrupts can
be disabled. For specific DMA features, see the DMA controller specification.
The SPI generates a request on the TX_DMA_REQ line each time the TX data is copied to the TX shift
register either from the TXBUF or from peripheral data bus (when TXBUF is empty).
The first TX_DMA_REQ pulse is generated when either of the following is true:
•
DMA REQ EN (SPIINT0[16]) is set to 1 while SPIEN (SPIGCR1[24]) is already 1.
•
SPIEN (SPIGCR1[24]) is set to 1 while DMA REQ EN (SPIINT0[16]) is already 1.
