System and Peripheral Control Registers
227
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.5.3.8
Peripheral Protection Set Register 3 (PPROTSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
. This register is shown in
and described in
.
NOTE:
Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-79. Peripheral Protection Set Register 3 (PPROTSET3) (offset = 2Ch)
31
0
PS[31-24]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -
n
= value after reset
Table 2-93. Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions
Bit
Field
Value
Description
31-0
PS[31-24]QUAD[3-0]
PROTSET
Peripheral select quadrant protection set.
0
Read:
The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write:
The bit is unchanged.
1
Read:
The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write:
The corresponding bit in PPROTSET3 and PPROTCLR3 registers is set to 1.
2.5.3.9
Peripheral Protection Clear Register 0 (PPROTCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in
.
This register is shown in
and described in
.
NOTE:
Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-80. Peripheral Protection Clear Register 0 (PPROTCLR0) (offset = 40h)
31
0
PS[7-0]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -
n
= value after reset
Table 2-94. Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions
Bit
Field
Value
Description
31-0
PS[7-0]QUAD[3-0]
PROTCLR
Peripheral select quadrant protection clear.
0
Read:
The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write:
The bit is unchanged.
1
Read:
The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write:
The corresponding bit in PPROTSET0 and PPROTCLR0 registers is cleared to 0.